SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com Extended Common-Mode RS-485 Transceivers Check for Samples: SN65HVD20, SN65HVD21, SN65HVD22, SN65HVD23, SN65HVD24 FEATURES 1 * * * * * * * Common-Mode Voltage Range (-20 V to 25 V) More Than Doubles TIA/EIA-485 Requirement Receiver Equalization Extends Cable Length, Signaling Rate (HVD23, HVD24) Reduced Unit-Load for up to 256 Nodes Bus I/O Protection to Over 16-kV HBM Failsafe Receiver for Open-Circuit, Short-Circuit and Idle-Bus Conditions Low Standby Supply Current 1-A Max More Than 100 mV Receiver Hysteresis APPLICATIONS * * Long Cable Solutions - Factory Automation - Security Networks - Building HVAC Severe Electrical Environments - Electrical Power Inverters - Industrial Drives - Avionics DESCRIPTION The transceivers in the HVD2x family offer performance far exceeding typical RS-485 devices. In addition to meeting all requirements of the TIA/EIA-485-A standard, the HVD2x family operates over an extended range of common-mode voltage, and has features such as high ESD protection, wide receiver hysteresis, and failsafe operation. This family of devices is ideally suited for long-cable networks, and other applications where the environment is too harsh for ordinary transceivers. These devices are designed for bidirectional data transmission on multipoint twisted-pair cables. Example applications are digital motor controllers, remote sensors and terminals, industrial process control, security stations, and environmental control systems. These devices combine a 3-state differential driver and a differential receiver, which operate from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected internally to form a differential bus port that offers minimum loading to the bus. This port features an extended common-mode voltage range making the device suitable for multipoint applications over long cable runs. HVD2x APPLICATION SPACE 100 HVD2x Devices Operate Over a Wider Common-Mode Voltage Range HVD23 -20 V Signaling Rate - Mbps HVD20 +25 V 10 HVD24 SUPER485 HVD21 1 RS485 -7 V HVD22 -20 V -15 V -10 V +12 V -5 V 0 5V 10 V 15 V 20 V 25 V 0.1 10 100 Cable Length - m 1000 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2010, Texas Instruments Incorporated SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The `HVD20 provides high signaling rate (up to 25 Mbps) for interconnecting networks of up to 64 nodes. The `HVD21 allows up to 256 connected nodes at moderate data rates (up to 5 Mbps). The driver output slew rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency noise emissions. The `HVD22 has controlled driver output slew rate for low radiated noise in emission-sensitive applications and for improved signal quality with long stubs. Up to 256 `HVD22 nodes can be connected at signaling rates up to 500 kbps. The `HVD23 implements receiver equalization technology for improved jitter performance on differential bus applications with data rates up to 25 Mbps at cable lengths up to 160 meters. The `HVD24 implements receiver equalization technology for improved jitter performance on differential bus applications with data rates in the range of 1 Mbps to 10 Mbps at cable lengths up to 1000 meters. The receivers also include a failsafe circuit that provides a high-level output within 250 microseconds after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence of any active transmitters on the bus. This feature prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. The SN65HVD2X devices are characterized for operation over the temperature range of -40C to 85C. PRODUCT SELECTION GUIDE CABLE LENGTH AND SIGNALING RATE (1) NODES MARKING SN65HVD20 Up to 50 m at 25 Mbps Up to 64 D: VP20 P: 65HVD20 SN65HVD21 Up to 150 m at 5 Mbps (with slew rate limit) Up to 256 D: VP21 P: 65HVD21 SN65HVD22 Up to1200 m at 500 kbps (with slew rate limit) Up to 256 D: VP22 P: 65HVD22 SN65HVD23 Up to 160 m at 25 Mbps (with receiver equalization) Up to 64 D: VP23 P: 65HVD23 SN65HVD24 Up to 500 m at 3 Mbps (with receiver equalization) Up to 256 D: VP24 P: 65HVD24 PART NUMBERS (1) Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter. AVAILABLE OPTIONS (1) 2 PLASTIC THROUGH-HOLE P-PACKAGE (JEDEC MS-001) PLASTIC SMALL-OUTLINE (1) D-PACKAGE (JEDEC MS-012) SN65HVD20P SN65HVD21P SN65HVD22P SN65HVD23P SN65HVD24P SN65HVD20D SN65HVD21D SN65HVD22D SN65HVD23D SN65HVD24D Add R suffix for taped and reeled carriers. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com Table 1. DRIVER FUNCTION TABLE HVD20, HVD21, HVD22 HVD23, HVD24 INPUT D ENABLE OUTPUTS DE A B H L X X OPEN H H L OPEN H H L Z Z H L H Z Z L INPUT D ENABLE OUTPUTS DE A B H L X X OPEN H H L OPEN H H L Z Z L L H Z Z H H = high level, L= low level, X = don't care, Z = high impedance (off), ? = indeterminate Table 2. RECEIVER FUNCTION TABLE DIFFERENTIAL INPUT VID = (VA - VB) ENABLE RE 0.2 V VID L -0.2 V < VID < 0.2 V L OUTPUT R H H (see Note VID -0.2 V L L X H Z X OPEN Z Open circuit L H Short Circuit L H Idle (terminated) bus L H (1) ) H = high level, L= low level, Z = high impedance (off) (1) If the differential input VID remains within the transition range for more than 250 s, the integrated failsafe circuitry detects a bus fault, and set the receiver output to a high state. See Figure 15. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) SN65HVD2X (2) -0.5 V to 7 V Voltage at any bus I/O terminal -27 V to 27 V Voltage input, transient pulse, A and B, (through 100 , see Figure 16) -60 V to 60 V Supply voltage , VCC -0.5 V to VCC+ 0.5 V Voltage input at any D, DE or RE terminal -10 mA to 10 mA Receiver output current, IO Human Body Model (3) Electrostatic dischargeElectrostatic discharge Charged-Device Model Machine Model (5) Continuous total power dissipation (4) A, B, GND 16 kV All pins 5 kV All pins 1.5 kV All pins 200 V See Thermal Table Junction temperature, TJ (1) (2) (3) (4) (5) 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Tested in accordance with JEDEC Standard 22, Test Method A115-A Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 3 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 4.5 5 5.5 V -20 25 V 2 VCC 0 0.8 Supply voltage, VCC Voltage at any bus I/O terminal High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID A, B D, DE, RE A with respect to B Driver Output current -25 25 -110 110 -8 8 Receiver UNIT V V mA Operating free-air temperature, TA (1) -40 85 C Junction temperature, TJ -40 130 C (1) Maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded. DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions PARAMETER TEST CONDITIONS VIK Input clamp voltage II = -18 mA VO Open-circuit output voltage A or B, No load |VOD(SS)| Steady-state differential output voltage MIN -1.5 4.2 RL = 54 , See Figure 1 1.8 2.5 With common-mode loading, See Figure 2 1.8 VOC(SS) Steady-state common-mode output voltage See Figure 1 VOC(SS) Change in steady-state common-mode output voltage, VOC(H) - VOC(L) See Figure 1 and Figure 4 -0.1 VOC(PP) Peak-to-peak common-mode output voltage, VOC(MAX) - VOC(MIN) RL = 54 , CL = 50 pF, See Figure 1 and Figure 4 0.35 VOD(RING) Differential output voltage over and under shoot RL = 54 , CL = 50 pF, See Figure 5 II Input current D, DE VO < = -7 V to 12 V, Other input = 0 V Output current with power off. High impedance state output current. VO < = -20 V to 25 V, Other input = 0 V Short-circuit output current COD Differential output capacitance (1) 4 VO = -20 V to 25 V, See Figure 9 -0.1 2.1 2.5 UNIT V VCC 3.3 See Figure 1 and Figure 3 MAX 0.75 No load (open circuit) Change in steady-state differential output voltage between logic states IOS ) 0 |VOD(SS)| IO TYP (1 V VCC V 0.1 V 2.9 V 0.1 V V 10% -100 100 HVD20, HVD23 -400 500 HVD21, HVD22, HVD24 -100 125 HVD20, HVD23 -800 1000 -200 250 -250 250 mA 20 pF HVD21, HVD22, HVD24 A A All typical values are at VCC = 5 V and 25C. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions PARAMETER tPLH Differential output propagation delay, low-to-high tPHL Differential output propagation delay, high-to-low tr Differential output rise time TEST CONDITIONS RL = 54 , CL = 50 pF, See Figure 3 RL = 54 , CL = 50 pF, See Figure 3 tf Differential output fall time tPZH Propagation delay time, high-impedance-to-high-level output tPHZ Propagation delay time, high-level output-to-high-impedance tPZL Propagation delay time, high-impedance-to-high-level output tPLZ Propagation delay time, high-level output-to-high-impedance td(standby) Time from an active differential output to standby td(wake) Wake-up time from standby to an active differential output RE at 0 V, See Figure 6 RE at 0 V, See Figure 7 MIN TYP (1) MAX 6 10 20 HVD20, HVD23 HVD21, HVD24 HVD22 20 32 60 160 280 500 12 HVD20, HVD23 2 6 HVD21, HVD24 20 40 60 200 400 600 HVD22 HVD20, HVD23 40 HVD21, HVD24 100 HVD22 300 HVD20, HVD23 40 HVD21, HVD24 100 HVD22 300 RE at VCC, See Figure 8 HVD20, HVD23 tsk(p ) Pulse skew | tPLH - tPHL| ns ns ns ns 2 s 8 s 2 HVD21, HVD24 6 HVD22 (1) UNIT ns 50 All typical values are at VCC = 5 V and 25C RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions PARAMETER VIT(+) Positive-going differential input voltage threshold VIT(-) Negative-going differential input voltage threshold VHYS Hysteresis voltage (VIT+ - VIT-) TEST CONDITIONS See Figure 10 VO = 0.4 V, IO = 8 mA VCM = -7 V to 12 V Positive-going differential input failsafe voltage threshold See Figure 15 VIT(F-) Negative-going differential input failsafe voltage threshold See Figure 15 VIK Input clamp voltage II = -18 mA VOH High-level output voltage VID = 200 mV, IOH = -8 mA, See Figure 11 VOL Low-level output voltage VID = -200 mV, IOL = 8 mA, See Figure 11 II Input resistanceInput resistance CID Differential input capacitance (1) 200 -200 -60 100 130 40 120 200 120 250 -40 VCM = -20 V to 25 V VCM = -7 V to 12 V -200 -120 VCM = -20 V to 25 V -250 -120 VI = -7 to 12 V, Other input = 0 V -400 HVD21, HVD22, HVD24 -100 125 VI = -20 to 25 V, Other input = 0 V HVD20, HVD23 -800 1000 HVD21, HVD22, HVD24 -200 250 -100 100 HVD21, HVD22, HVD24 96 VID = 0.5 + 0.4 sine (2 x 1.5 x 106t) mV mV V 0.4 24 mV V 4 HVD20, HVD23 UNIT mV -1.5 RE RI MAX 60 HVD20, HVD23 Bus input current (power on or power off) Input current TYP (1) VO = 2.4 V, IO = -8 mA VIT(F+) II(BUS) MIN V 500 A A k 20 pF All typical values are at 25C. Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 5 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPLH TEST CONDITIONS Propagation delay time, low-to-high level output See Figure 11 tPHL Propagation delay time high-to low level output tr tf Receiver output rise time Receiver output fall time tPZH Receiver output enable time to high level tPHZ Receiver output disable time from high level tPZL Receiver output enable time to low level tPLZ Receiver output disable time from low level tr(standby) Time from an active receiver output to standby tr(wake) Wake-up time from standby to an active receiver output tsk(p) Pulse skew |tPLH - tPHL| tp(set) Delay time, bus fail to failsafe set tp(reset) Delay time, bus recovery to failsafe reset TYP MAX HVD20, HVD23 MIN 16 35 HVD21, HVD22, HVD24 25 50 2 4 ns 90 120 ns 16 35 90 120 16 35 See Figure 11 See Figure 12 See Figure 13 2 See Figure 14, DE at 0 V UNIT ns ns s 8 5 250 See Figure 15, pulse rate = 1 kHz 350 50 s ns RECEIVER EQUALIZATION CHARACTERISTICS (1) over recommended operating conditions PARAMETER MIN TYP (2) TEST CONDITIONS 0m 100 m 25 Mbps 150 m 200 m 200 m tj(pp) Peudo-random NRZ code with a bit Peak-to-peak pattern length of 216 - 1, Beldon eye-pattern jitter 3105A cable, See Figure 27 10 Mbps 300 m 5 Mbps 3 Mbps 1 Mbps (1) (2) 6 250 m 500 m 500 m 1000 m HVD23 2 HVD20 6 HVD23 3 HVD20 15 HVD23 4 HVD20 27 HVD23 8 HVD20 22 HVD23 8 HVD20 34 HVD23 15 HVD20 49 HVD23 27 HVD21 128 HVD24 18 HVD20 93 HVD21 103 HVD23 90 HVD24 16 HVD21 216 HVD24 62 MAX UNIT ns ns ns ns ns ns ns ns ns ns The HVD20 and HVD21 do not have receiver equalization, but are specified for comparison. All typical values are at VCC = 5 V, and temperature = 25C. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com SUPPLY CURRENT over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Driver enabled (DE at VCC), Receiver enabled (RE at 0 V), No load, VI = 0 V or VCC ICC Supply current Driver enabled (DE at VCC), Receiver disabled (RE at VCC), No load, VI = 0 V or VCC Driver disabled (DE at 0 V), Receiver enabled (RE at 0 V), No load Driver disabled (DE at 0 V), Receiver disabled (RE at VCC) D open Copyright (c) 2002-2010, Texas Instruments Incorporated MIN TYP MAX HVD20 6 9 HVD21 8 12 HVD22 6 9 HVD23 7 11 HVD24 10 14 HVD20 5 8 HVD21 7 11 HVD22 5 8 HVD23 5 9 HVD24 8 12 HVD20 4 7 HVD21 5 8 HVD22 4 7 HVD23 4.5 9 HVD24 5.5 10 All HVD2x 1 Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 UNIT mA mA mA A 7 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS RE Inputs DE Input D Inputs (HVD20, 21, 22) D Inputs (HVD23, 24) VCC VCC 100 k 1 k 1 k Input Input 100 k 9V 9V A Input B Input VCC VCC R1 R3 R1 R3 Input Input 29 V R2 R2 29 V 29 V A and B Outputs R Output VCC VCC 5 Output Output 9V 29 V 8 R1/R2 R3 HVD20, 23 9 k 45 k HVD21, 22, 24 36 k 180 k Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION NOTE: Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and fall time <6 ns, pulse rate 100 kHz, 50% duty cycle, Zo = 50 (unless otherwise specified). IO II 27 VOD 0 V or 3 V 50 pF 27 IO VOC Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading 375 IO VOD 0 V or 3 V 60 IO 375 VTEST = -20 V to 25 V VTEST Figure 2. Driver Test Circuit, VOD With Common-Mode Loading 3V INPUT VOD RL = 54 Signal Generator 1.5 V 90% 0V tPHL VOD(H) 10% VOD(L) tPLH CL = 50 pF 50 1.5 V 0V OUTPUT tr tf Figure 3. Driver Switching Test Circuit and Waveforms 27 A VA D Signal Generator 50 B 27 -3.25 V VB 50 pF -1.75 V VOC(PP) VOC VOC(SS) VOC Figure 4. Driver VOC Test Circuit and Waveforms Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 9 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VOD(SS) VOD(RING) VOD(PP) 0 V Differential VOD(RING) VOD(SS) NOTE: VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L) steady state values. Figure 5. VOD(RING) Waveform and Definitions A D 0 V or 3 V 3 V if Testing A Output 0 V if Testing B Output DE Signal Generator S1 3V Output B DE CL = 50 pF RL = 110 1.5 V 1.5 V 0.5 V tPZH 0V VOH Output 2.5 V 50 tPHZ VOff 0 Figure 6. Driver Enable/Disable Test, High Output 5V S1 D 0 V or 3 V 0 V if Testing A Output 3 V if Testing B Output DE Signal Generator RL = 110 3V Output CL = 50 pF DE 1.5 V 1.5 V 0V tPZL Output 50 tPLZ 5V 2.5 V VOL 0.5 V Figure 7. Driver Enable/Disable Test, Low Output 10 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 3V DE 1.5 V 0V A D 0 V or 3 V CL = 50 pF RL = 54 VOD B 1.5 V V OD DE Signal Generator td(Wake) td(Standby) 0.2 V 50 Figure 8. Driver Standby/Wake Test Circuit and Waveforms IOS VO Voltage Source Figure 9. Driver Short-Circuit Test IO VID VO Figure 10. Receiver DC Parameter Definitions Signal Generator 50 Input B VID A B Signal Generator 50 R CL = 15 pF IO VO 1.5 V 50% Input A tPLH Output 90% 1.5 V tr 0V tPHL VOH 10% V OL tf Figure 11. Receiver Switching Test Circuit and Waveforms Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 11 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) D VCC VCC DE A 54 B R 3V RE 0V 1.5 V 0V CL = 15 pF RE Signal Generator 1 k tPZH tPHZ VOH VOH -0.5 V 50 1.5 V R GND Figure 12. Receiver Enable Test Circuit and Waveforms, Data Output High 0V VCC D DE A 54 B R 3V RE 5V 1.5 V 0V CL = 15 pF RE Signal Generator 1 k tPZL tPLZ VCC 50 1.5 V R VOL +0.5 V VOL Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output Low VCC Switch Down for V(A) = 1.5 V, Switch Up for V(A) = -1.5 V A 1.5 V or -1.5 V R B 3V 1 k CL = 15 pF RE 1.5 V 0V RE Signal Generator tr(Standby) tr(Wake) 50 5V R 1.5 V VOH 0.5 V VOL +0.5 V 0V VOH VOL Figure 14. Receiver Standby and Wake Test Circuit and Waveforms 12 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Bus Data Valid Region 200 mV Bus Data Transition Region -40 mV VID -200 mV -1.5 V Bus Data Valid Region tp(SET) tp(RESET) VOH R 1.5 V VOL Figure 15. Receiver Active Failsafe Definitions and Waveforms VTEST 100 0V Pulse Generator, 15 ms Duration, 1% Duty Cycle 1.5 ms 15 ms V TEST Figure 16. Test Circuit and Waveforms, Transient Overvoltage Test PIN ASSIGNMENTS D or P PACKAGE (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND LOGIC DIAGRAM R RE DE D Copyright (c) 2002-2010, Texas Instruments Incorporated 1 2 3 6 A 7 B 4 Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 13 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com THERMAL INFORMATION SN65HVD2x THERMAL METRIC (1) Junction-to-case(top) thermal resistance JB Junction-to-board thermal resistance JT Junction-to-top characterization parameter JB Junction-to-board characterization parameter JC(bottom) (4) (5) (6) (7) PINS 78.1 52.5 56.5 57.6 50.4 38.6 4.1 19.1 32.6 31.9 nA n/A (3) JC(top) (3) PDIP (P) 8 PINS Junction-to-ambient thermal resistance (2) JA (1) (2) SOIC (D) (4) (5) Junction-to-case(bottom) thermal resistance (6) (7) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. POWER DISSIPATION PARAMETERS TEST CONDITIONS HVD20 HVD21 Typical HVD22 HVD23 VCC = 5 V, TJ = 25C, RL = 54 , CL = 50 pF (driver), CL = 15 pF (receiver), 50% Duty cycle square-wave signal, Driver and receiver enabled HVD24 Device Power dissipation, PD HVD20 HVD21 Worst case HVD22 HVD23 HVD24 VCC = 5.5 V, TJ = 125C, RL = 54 , CL = 50 pF, CL = 15 pF (receiver), 50% Duty cycle square-wave signal, Driver and receiver enabled VALUE 25 Mbps 295 5 Mbps 260 500 kbps 233 25 Mbps 302 5 Mbps 267 25 Mbps 408 5 Mbps 342 500 kbps 300 25 Mbps 417 5 Mbps 352 Thermal shut down junction temperature, TSD 14 Submit Documentation Feedback 170 UNIT mW mW C Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS HVD20, HVD23 BUS PIN CURRENT vs BUS PIN VOLTAGE HVD21, HVD22, HVD24 BUS PIN CURRENT vs BUS PIN VOLTAGE 150 600 DE = 0 V DE = 0 V 100 Bus Pin Current - m A Bus Pin Current - m A 400 200 VCC = 0 V 0 VCC = 5 V 200 VCC = 0 V 0 VCC = 5 V 50 100 400 600 -30 50 -20 0 -10 10 20 150 -30 30 -20 Bus Pin Voltage - V Figure 18. SUPPLY CURRENT vs SIGNALING RATE DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs DRIVER LOAD CURRENT 30 5 VCC = 5 V, DE = RE = VCC, LOAD = 54 , 50 pF HVD20 VOD - Driver Differential Output Voltage - V ICC - Supply Current - mA 20 Figure 17. 65 HVD22 HVD21 60 55 50 45 40 0.1 10 Bus Pin Voltage - V 75 70 0 -10 4.5 VCC = 5.5 V 4 3.5 VCC = 5 V 3 2.5 2 VCC = 4.5 V 1.5 1 0.5 0 10 1 Signaling Rate - Mbps Figure 19. Copyright (c) 2002-2010, Texas Instruments Incorporated 100 0 10 20 30 40 50 60 IL - Driver Load Current - mA 70 80 Figure 20. Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 15 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) HVD20, HVD23 PEAK-TO-PEAK JITTER vs CABLE LENGTH RECEIVER OUTPUT VOLTAGE vs DIFFERENTAL INPUT VOLATGE 30 6 VIT(-) 25 VCM = 25 V VCM = 25 V 4 VCM = 0 V VCM = 0 V 3 2 VCM = 20 V VCM = 20 V 1 Peak-to-Peak Jitter - ns VO - Receiver Output Voltage - V 5 VIT(+) 0 -0.1 0.1 VID - Differential Input Voltage - V 10 HVD23 = 25 Mbps 120 140 160 Cable Length - m Figure 21. Figure 22. HVD20, HVD21, HVD23, HVD24 PEAK-TO-PEAK JITTER vs CABLE LENGTH HVD20, HVD23 PEAK-TO-PEAK JITTER vs SIGNALING RATE HVD21 = 10 Mbps 110 40 HVD20 = 10 Mbps 30 HVD23 = 10 Mbps 20 90 VCC = 5 V, TA = 25C, VIC = 2.5 V, Cable: Belden 3105A 70 50 30 10 HVD24: 500 m Cable HVD24 = 10 Mbps 220 240 260 Cable Length - m Figure 23. 16 200 HVD21: 500 m Cable 50 0 200 180 130 VCC = 5 V, TA = 25C, VIC = 2.5 V, Cable: Belden 3105A Peak-to-Peak Jitter - ns Peak-to-Peak Jitter - ns 15 0 100 0.2 70 60 HVD20 = 25 Mbps 20 5 0 1 -0.2 VCC = 5 V, TA = 25C, VIC = 2.5 V, Cable: Belden 3105A Submit Documentation Feedback 280 300 10 3 3.5 4 4.5 Signaling Rate - Mbps 5 Figure 24. Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The HVD2x family of devices integrates a differential receiver and differential driver with additional features for improved performance in electrically-noisy, long-cable, or other fault-intolerant applications. The receiver hysteresis (typically 130 mV) is much larger than found in typical RS-485 transceivers. This helps reject spurious noise signals which would otherwise cause false changes in the receiver output state. Slew rate limiting on the driver outputs (SN65HVD21, 22, and 24) reduces the high-frequency content of signal edges. This decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and the main bus line. Designers should consider the maximum signaling rate and cable length required for a specific application, and choose the transceiver best matching those requirements. When DE is low, the differential driver is disabled, and the A and B outputs are in high-impedance states. When DE is high, the differential driver is enabled, and drives the A and B outputs according to the state of the D input.s When RE is high, the differential receiver output buffer is disabled, and the R output is in a high-impedance state. When RE is low, the differential receiver is enabled, and the R output reflects the state of the differential bus inputs on the A and B pins. If both the driver and receiver are disabled, (DE low and RE high) then all nonessential circuitry, including auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. This reduces power consumption to less than 5W. When either enable input is asserted, the circuitry again becomes active. In addition to the primary differential receiver, these devices incorporate a set of comparators and logic to implement an active receiver failsafe feature. These components determine whether the differential bus signal is valid. Whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, If the differential input remains within the transition range for more than 250 microseconds, the timer expires and set the receiver output to the high state. If a valid bus input (high or low) is received at any time, the receiver output reflects the valid bus state, and the timer is reset. (V A-V B ) : Not High + - Bus Input Invalid (VA-V B) : Not Low Timer 250 ms R RE 1 120 mV + 120 mV Active Filters 2 STANDBY 3 DE 6 D Slew Rate Control 4 7 A B Figure 25. Function Block Diagram Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 17 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com Figure 26. HVD22 Receiver Operation With 20-V Offset on Input Signal k0 (DC loss) p1 (MHz) k1 p2 (MHz) k2 p3 (MHz) k3 Similar to 160m of Belden 3105A 0.95 0.25 0.3 3.5 0.5 15 1 Similar to 250m of Belden 3105A 0.9 0.25 0.4 3.5 0.7 12 1 Similar to 500m of Belden 3105A 0.8 0.25 0.6 2.2 1 8 1 Similar to 1000m of Belden 3105A 0.6 0.3 1 3 1 6 1 H(s) = k0 (1-k1) + k1p1 (s + p1) (1-k2) + k p 2 2 (s + p2) (1-k3) + Signal Generator k p 3 3 (s + p3) H(s) Figure 27. Cable Attenuation Model for Jitter Measurements 18 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com INTEGRATED RECEIVER EQUALIZATION USING THE HVD23 Figure 28 illustrates the benefits of integrated receiver equalization as implemented in the HVD23 transceiver. In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). Channel 2 (bottom) shows the output of the receiver. Figure 28. HVD23 Receiver Performance at 25 Mbps Over 150 Meter Cable Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 19 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com INTEGRATED RECEIVER EQUALIZATION USING THE HVD24 Figure 29 illustrates the benefits of integrated receiver equalization as implemented in the HVD24 transceiver. In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the bit stream. Channel 2 (middle) shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). Channel 3 (bottom) shows the output of the receiver. Figure 29. HVD24 Receiver Performance at 5 Mbps Over 500 Meter Cable 20 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com NOISE CONSIDERATIONS FOR EQUALIZED RECEIVERS The simplest way of overcoming the effects of cable losses is to increase the sensitivity of the receiver. If the maximum attenuation of frequencies of interest is 20 dB, increasing the receiver gain by a factor of ten compensates for the cable. However, this means that both signal and noise are amplified. Therefore, the receiver with higher gain is more sensitive to noise and it is important to minimize differential noise coupling to the equalized receiver. Differential noise is crated when conducted or radiated noise energy generates more voltage on one line of the differential pair than the other. For this to occur from conducted or electric far-field noise, the impedance to ground of the lines must differ. For noise frequency out to 50 MHz, the input traces can be treated as a lumped capacitance if the receiver is approximately 10 inches or less from the connector. Therefore, matching impedance of the lines is accomplished by matching the lumped capacitance of each. The primary factors that affect the capacitance of a trace are in length, thickness, width, dielectric material, distance from the signal return path, stray capacitance, and proximity to other conductors. It is difficult to match each of the variables for each line of the differential pair exactly, but a reasonable effort to do so keeps the lines balanced and less susceptible to differential noise coupling. Another source of differential noise is from near-field coupling. In this situation, an assumption of equal noise-source impedance cannot be made as in the far-field. Familiarly known as crosstalk, more energy from a nearby signal is coupled to one line of the differential pair. Minimization of this differential noise is accomplished by keeping the signal pair close together and physical separation from high-voltage, high-current, or high-frequency signals. In * * * * * summary, follow these guidelines in board layout for keeping differential noise to a minimum. Keep the differential input traces short. Match the length, physical dimensions, and routing of each line of the pair. Keep the lines close together. Match components connected to each line. Separate the inputs from high-voltage, high-frequency, or high-current signals. Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 21 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com TEST MODE DRIVER DISABLE If the input signal to the D pin is such that: 1. the signal has signaling rate above 4 Mbps (for the `HVD21 and `HVD24) 2. the signal has signaling rate above 6 Mbps (for the `HVD20 and `HVD23) 3. the signal has average amplitude between 1.2 V and 1.6 V (1.4 V 200 mV) 4. the average signal amplitude remains in this range for 100 sec or longer, then the driver may activate a test-mode during which the driver outputs are temporarily disabled. This can cause loss of transmission of data during the period that the device is in the test-mode. The driver will be re-enabled and resume normal operation whenever the above conditions are not true. The device is not damaged by this test mode. Although rare, there are combinations of specific voltage levels and input data patterns within the operating conditions of the HVD2x family which may lead to a temporary state where the driver outputs are disabled for a period of time. Observations: 1. The conditions for inadvertently entering the test mode are dependent on the levels, duration, and duty cycle of the logic signal input to the D pin. Operating input levels are specified as greater than 2 V for a logic HIGH input, and less than 0.8V for a logic LOW input. Therefore, a valid steady-state logic input will not cause the device to activate the test mode 2. Only input signals with frequency content above 2 MHz (4 Mbps) have a possibility of activating the test mode. Therefore, this issue should not affect the normal operation of the HVD22 (500 kbps). 3. For operating signaling rates of 4 Mbps (or above), the conditions stated above must remain true over a period of: 4 Mbps x 100 sec = 400 bits. Therefore, a normal short message will not inadvertently activate the test model 4. One example of an input signal which may cause the test mode to activate is a clock signal with frequency 3 MHz and 50% duty cycle (symmetric HIGH and LOW half-cycles) with logic HIGH levels of 2.4 V and logic LOW levels of 0.4 V. This signal applied to the D pin as a driver input would meet the criteria listed above, and might cause the test-mode to activate, which would disable the driver. Note that this example situation might occur if the clock signal were generated by a microcontroller or logic chip with a 2.7 V-supply. 22 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24 SLLS552E - DECEMBER 2002 - REVISED MAY 2010 www.ti.com REVISION HISTORY Changes from Original (December 2002) to Revision A * Page Changed tPZH, tPHZ, tPZL, and tPLZ - From a MAX value of 120 To include TYP and MAX values for each entry (RECEIVER SWITCHING CHARACTERISTICS table) ........................................................................................................ 6 Changes from Revision A (March 2003) to Revision B Page * Added VIK TYP Value of 0.75V (DRIVER ELECTRICAL CHARACTERISTICS table) ......................................................... 4 * Deleted VIT(F+) - VCM = -20 V to 25 V MIN value (RECEIVER ELECTRICAL CHARACTERISTICS table) ....................... 5 * Added RECEIVER EQUALIZATION CHARACTERISTICS table ......................................................................................... 6 * Changed A Input circuit in the EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS ........................................ 8 * Added Figure 22, Figure 23, and Figure 24 to the TYPICAL CHARACTERISTICS .......................................................... 15 * Changed the INTEGRATED RECEIVER EQUALIZATION USING THE HVD23 section .................................................. 19 * Changed the INTEGRATED RECEIVER EQUALIZATION USING THE HVD24 section .................................................. 20 Changes from Revision B (June 2003) to Revision C Page * Added the THERMAL CHARACTERISTICS table ............................................................................................................. 14 * Added the THEORY OF OPERATION section ................................................................................................................... 17 * Added the NOISE CONSIDERATIONS FOR EQUALIZED RECEIVERS section ............................................................. 21 Changes from Revision C (September 2003) to Revision D Page * Added Conditions note to the ABSOLUTE MAXIMUM RATINGS table "over operating free-air temperature range (unless otherwise noted)" ..................................................................................................................................................... 3 * Deleted Storage temperature, Tstg from the ABSOLUTE MAXIMUM RATINGS table ......................................................... 3 * Added Receiver output current, IO to the ABSOLUTE MAXIMUM RATINGS table ............................................................. 3 Changes from Revision D (April 2005) to Revision E Page * Changed IO - Added test condition and values per device number (DRIVER ELECTRICAL CHARACTERISTICS table) ..................................................................................................................................................................................... 4 * Replaced the Dissipation Rating table with the THERMAL INFORMATION table ............................................................. 14 * Changed the THERMAL CHARACTERISTICS table to POWER DISSIPATION table ...................................................... 14 * Added the TEST MODE DRIVER DISABLE section .......................................................................................................... 22 Copyright (c) 2002-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 23 PACKAGE OPTION ADDENDUM www.ti.com 4-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65HVD20D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD20DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD20DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD20DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD20P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD20PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD21D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD21DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD21DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD21DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD21P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD21PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD22D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD22DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD22DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD22DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD22P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD22PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD23D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD23DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD23DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD23DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD23P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD23PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD24D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 4-May-2010 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65HVD24DG4 ACTIVE SOIC D 8 SN65HVD24DR ACTIVE SOIC D SN65HVD24DRG4 ACTIVE SOIC SN65HVD24P ACTIVE SN65HVD24PE4 ACTIVE 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-May-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65HVD20DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD21DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD22DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD23DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD24DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-May-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD20DR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD21DR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD22DR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD23DR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD24DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated