GS8342D08/09/18/36AE-333/300/250/200/167
36Mb SigmaQuad-II
Burst of 4 SRAM
167 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.05 12/2007 1/36 © 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write (x36, x18, and x9) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb
and 144Mb devices
SigmaQuad™ Family Overview
The GS8342D08/09/18/36AE are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342D08/18/36AE SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342D08/09/18/36AE SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock quasi independently with the C and C
clock inputs. C and C are also independent single-ended clock
inputs, not differential inputs. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead.
Because Separate I/O SigmaQuad-II B4 RAMs always transfer
data in four packets, A0 and A1 are internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfers. Because the LSBs are tied off internally,
the address field of a SigmaQuad-II B4 RAM is always two
address pins less than the advertised index depth (e.g., the 2M
x 18 has a 512K addressable index).
Parameter Synopsis
- 333 -300 -250 -200 -167
tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns
tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.50 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 2/36 © 2006, GSI Technology
1M x 36 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ NC NC WBW2 KBW1 RSA NC CQ
B Q27 Q18 D18 SA BW3 KBW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1
P Q35 D35 Q26 SA SA CSA SA Q9 D0 Q0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35
2. A2, A3, and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Expansion Addresses
A3 72Mb
A10 144Mb
A2 288Mb
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 3/36 © 2006, GSI Technology
2M x 18 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ NC SA WBW1 KNC RSA NC CQ
B NC Q9 D9 SA NC KBW0 SA NC NC Q8
C NC NC D10 VSS SA NC SA VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS SA SA SA VSS NC NC D1
P NC NC Q17 SA SA CSA SA NC D0 Q0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. A2, A7, and A10 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Expansion Addresses
A10 72Mb
A2 144Mb
A7 288Mb
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 4/36 © 2006, GSI Technology
4M x 9 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ NC SA WNC KNC RSA SA CQ
B NC NC NC SA NC KBW0 SA NC NC Q4
C NC NC NC VSS SA NC SA VSS NC NC D4
D NC D5 NC VSS VSS VSS VSS VSS NC NC NC
E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1
M NC NC NC VSS VSS VSS VSS VSS NC NC D1
N NC D8 NC VSS SA SA SA VSS NC NC NC
P NC NC Q8 SA SA CSA SA NC D0 Q0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8.
2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Expansion Address
A2 72Mb
A7 144Mb
B5 288Mb
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 5/36 © 2006, GSI Technology
4M x 8 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ NC SA WNW1 KNC RSA SA CQ
B NC NC NC SA NC KNW0 SA NC NC Q3
C NC NC NC VSS SA NC SA VSS NC NC D3
D NC D4 NC VSS VSS VSS VSS VSS NC NC NC
E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0
M NC NC NC VSS VSS VSS VSS VSS NC NC D0
N NC D7 NC VSS SA SA SA VSS NC NC NC
P NC NC Q7 SA SA CSA SA NC NC NC
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. A2, A7, and B5 are reserved for future use as an address pin for higher density devices. They are not connected to the die on this device.
They may be left floating or be treated as an MCL pin (Must Connect Low) to assure the site will successfully accomodate a future, higher
density device. These pins may be marked as VSS, NC, or MCL by some vendors of compatible SRAMs.
Expansion Address
A2 72Mb
A7 144Mb
B5 288Mb
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 6/36 © 2006, GSI Technology
Notes:
1. NC = Not Connected to die or any other pin
2. C, C, K, or K cannot be set to VREF voltage.
Pin Description Table
Symbol Description Type Comments
SA Synchronous Address Inputs Input —
NC No Connect — —
RSynchronous Read Input Active Low
WSynchronous Write Input Active Low
BW0–BW3 Synchronous Byte Writes Input Active Low
x9/x18/x36 only
NW0–NW1 Nybble Write Control Pin Input Active Low
x8 only
KInput Clock Input Active High
KInput Clock Input Active Low
COutput Clock Input Active High
COutput Clock Input Active Low
TMS Test Mode Select Input —
TDI Test Data Input Input —
TCK Test Clock Input Input —
TDO Test Data Output Output —
VREF HSTL Input Reference Voltage Input —
ZQ Output Impedance Matching Input Input —
Qn Synchronous Data Outputs Output
Dn Synchronous Data Inputs Input
Doff Disable DLL when low Input Active Low
CQ Output Echo Clock Output —
CQ Output Echo Clock Output —
VDD Power Supply Supply 1.8 V Nominal
VDDQ Isolated Output Buffer Supply Supply 1.5 or 1.8 V Nominal
VSS Power Supply: Ground Supply —
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 7/36 © 2006, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data
can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following
rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,
and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read
port deselect cycle.
SigmaQuad-II B4 Double Data Rate SRAM Read First
Read A NOP Read B Write C Read D Write E NOP
A B C D E
CC+1 C+2 C+3 EE+1
CC+1 C+2 C+3 EE+1
AA+1 A+2 A+3 BB+1 B+2 B+3 DD+1 D+2
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 8/36 © 2006, GSI Technology
SigmaQuad-II B4 SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous
command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge
of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.
SigmaQuad-II B4 Double Data Rate SRAM Write First
Write A NOP Read B Write C Read D Write E NOP
A B C D E
AA+1 A+2 A+3 CC+1 C+2 C+3 EE+1 E+
AA+1 A+2 A+3 CC+1 C+2 C+3 EE+1 E+
BB+1 B+2 B+3 DD+1 D+2
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 9/36 © 2006, GSI Technology
Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. Apply VDD.
1b. Apply VDDQ.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30 ns. 1024 cycles of clean K clocks are always required to re-
lock the DLL after reset.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar ).
• The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired operating clock frequency.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during
the initial stage.
Power-Up Sequence (Doff controlled)
Power-Up Sequence (Doff tied High)
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Power UP Interval Unstable Clocking Interval DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
Power UP Interval Unstable Clocking Interval Stop Clock Interval DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
30ns Min
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Rev: 1.05 12/2007 10/36 © 2006, GSI Technology
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.
Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample
Time BW0 BW1 D0–D8 D9–D17
Beat 1 0 1 Data In Don’t Care
Beat 2 1 0 Don’t Care Data In
Beat 3 0 0 Data In Data In
Beat 4 1 0 Don’t Care Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Written Unchanged Unchanged Written Written Written Unchanged Written
Beat 1 Beat 2 Beat 3 Beat 4
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Rev: 1.05 12/2007 11/36 © 2006, GSI Technology
Example Four Bank Depth Expansion Schematic
A
K
R
W
A0–An
K
W0
D1–Dn
Bank 0 Bank 1 Bank 2 Bank 3
R0
D
A
K
W
D
A
K
W
D
A
K
W
D
RRR
QQQ Q
CC CC
Q1–Qn
C
W1
R1
W2
R2
W3
R3
Note:
For simplicity BWn, NWn, K, and C are not shown.
CQ CQ CQ CQ
CQ0
CQ1
CQ2
CQ3
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Rev: 1.05 12/2007 12/36 © 2006, GSI Technology
Σ2x2B4 SigmaQuad-II SRAM Depth Expansion
Read A Write B Read C Write D Read E Write F NOP
A B C D E F
DD+1 D+2 D+3
DD+1 D+2 D+3
BB+1 B+2 B+3 F F+1 F
BB+1 B+2 B+3 F F+1 F
AA+1 A+2 A+3 EE+1 E+2
CC+1 C+2 C+3
K
K
Address
R(1)
R(2)
W(1)
W(2)
BWx(1)
D(1)
BWx(2)
D(2)
C[1]
C[1]
Q(1)
CQ(1)
CQ[1]
C[2]
C[2]
Q(2)
CQ[2]
CQ[2]
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Rev: 1.05 12/2007 13/36 © 2006, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Separate I/O SigmaQuad-II B4 SRAM Truth Table
Previous
Operation A R W Current
Operation D D D D Q Q Q Q
K ↑
(tn-1)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K ↑
(tn)
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
Deselect X 1 1 Deselect X X — — Hi-Z Hi-Z — —
Write X 1 X Deselect D2 D3 — — Hi-Z Hi-Z — —
Read X X 1 Deselect X X — — Q2 Q3 — —
Deselect V 1 0 Write D0 D1 D2 D3 Hi-Z Hi-Z — —
Deselect V 0 X Read X X — — Q0 Q1 Q2 Q3
Read V X 0 Write D0 D1 D2 D3 Q2 Q3 — —
Write V 0 X Read D2 D3 — — Q0 Q1 Q2 Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when
preceded by a Read command.
6. Users should not clock in metastable addresses.
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Rev: 1.05 12/2007 14/36 © 2006, GSI Technology
Byte Write Clock Truth Table
BW BW BW BW Current Operation D D D D
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
K ↑
(tn)
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
T T T T Write
Dx stored if BWn = 0 in all four data transfers D0 D2 D3 D4
T F F F Write
Dx stored if BWn = 0 in 1st data transfer only D0 XXX
F T F F Write
Dx stored if BWn = 0 in 2nd data transfer only XD1 X X
F F T F Write
Dx stored if BWn = 0 in 3rd data transfer only X X D2 X
F F F T Write
Dx stored if BWn = 0 in 4th data transfer only X X X D3
F F F F Write Abort
No Dx stored in any of the four data transfers X X X X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
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Rev: 1.05 12/2007 15/36 © 2006, GSI Technology
x36 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35
1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care
0 1 1 1 Data In Don’t Care Don’t Care Don’t Care
1 0 1 1 Don’t Care Data In Don’t Care Don’t Care
0 0 1 1 Data In Data In Don’t Care Don’t Care
1 1 0 1 Don’t Care Don’t Care Data In Don’t Care
0 1 0 1 Data In Don’t Care Data In Don’t Care
1 0 0 1 Don’t Care Data In Data In Don’t Care
0 0 0 1 Data In Data In Data In Don’t Care
1 1 1 0 Don’t Care Don’t Care Don’t Care Data In
0 1 1 0 Data In Don’t Care Don’t Care Data In
1 0 1 0 Don’t Care Data In Don’t Care Data In
0 0 1 0 Data In Data In Don’t Care Data In
1 1 0 0 Don’t Care Don’t Care Data In Data In
0 1 0 0 Data In Don’t Care Data In Data In
1 0 0 0 Don’t Care Data In Data In Data In
0 0 0 0 Data In Data In Data In Data In
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1 D0–D8 D9–D17
1 1 Don’t Care Don’t Care
0 1 Data In Don’t Care
1 0 Don’t Care Data In
0 0 Data In Data In
x09 Byte Write Enable (BWn) Truth Table
BW0 D0–D8
1Don’t Care
0Data In
1Don’t Care
0Data In
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Rev: 1.05 12/2007 16/36 © 2006, GSI Technology
Nybble Write Clock Truth Table
NW NW NW NW Current Operation D D D D
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
K ↑
(tn)
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
T T T T Write
Dx stored if NWn = 0 in all four data transfers D0 D2 D3 D4
T F F F Write
Dx stored if NWn = 0 in 1st data transfer only D0 XXX
F T F F Write
Dx stored if NWn = 0 in 2nd data transfer only XD1 X X
F F T F Write
Dx stored if NWn = 0 in 3rd data transfer only X X D2 X
F F F T Write
Dx stored if NWn = 0 in 4th data transfer only X X X D3
F F F F Write Abort
No Dx stored in any of the four data transfers X X X X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1 D0–D3 D4–D7
1 1 Don’t Care Don’t Care
0 1 Data In Don’t Care
1 0 Don’t Care Data In
0 0 Data In Data In
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State Diagram
Power-Up
Read NOP
Load New
Read Address
D Count = 0
DDR Read
D Count = D Count + 1
Write NOP
Load New
Write Address
D Count = 0
DDR Write
D Count = D Count + 1
WRITE
READ
READ
D Count = 2
WRITE
D Count = 2
READ WRITE
Always Always
READ
D Count = 2
Notes:
1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1.
2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is
true for “WRITE” and “WRITE”.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
READ
D Count = 1 Always
Increment
Read Address
WRITE
D Count = 2
Increment
Write Address
WRITE
D Count = 1
Always
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Recommended Operating Conditions
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 2.9 V
VDDQ Voltage in VDDQ Pins –0.5 to VDD V
VREF Voltage in VREF Pins –0.5 to VDDQ V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V
IIN Input Current on Any Pin +/–100 mA dc
IOUT Output Current on Any I/O Pin +/–100 mA dc
TJMaximum Junction Temperature 125 oC
TSTG Storage Temperature –55 to 125 oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Power Supplies
Parameter Symbol Min. Typ. Max. Unit
Supply Voltage VDD 1.7 1.8 1.95 V
I/O Supply Voltage VDDQ 1.4 —VDD V
Reference Voltage VREF 0.68 —0.95 V
Notes:
1. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF
, followed by signal
inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD.
2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The
part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance
specifications quoted are evaluated for worst case in the temperature range marked on the device.
Operating Temperature
Parameter Symbol Min. Typ. Max. Unit
Ambient Temperature
(Commercial Range Versions) TA025 70 °C
Ambient Temperature
(Industrial Range Versions) TA–40 25 85 °C
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HSTL I/O DC Input Characteristics
Parameter Symbol Min Max Units Notes
DC Input Logic High VIH (dc) VREF + 0.1 VDD + 0.3 V 1
DC Input Logic Low VIL (dc) –0.3 VREF – 0.1 V 1
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
3. VIL (Min)DC = –0.3 V, VIL(Min)AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics
Parameter Symbol Min Max Units Notes
AC Input Logic High VIH (ac) VREF + 200 —mV 3,4
AC Input Logic Low VIL (ac) —VREF – 200 mV 3,4
VREF Peak to Peak AC Voltage VREF (ac) —5% VREF (DC) mV 1
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
20% tKHKH
VSS – 1.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKHKH
VDD + 1.0 V
50%
VDD
VIL
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AC Test Load Diagram
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Output Capacitance COUT VOUT = 0 V 6 7 pF
Clock Capacitance CCLK VIN = 0 V 5 6 pF
Note:
This parameter is sample tested.
AC Test Conditions
Parameter Conditions
Input high level 1.25 V
Input low level 0.25 V
Max. input slew rate 2 V/ns
Input reference level 0.75 V
Output reference level VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
Input and Output Leakage Characteristics
Parameter Symbol Test Conditions Min. Max Notes
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA
Doff IINDOFF
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–2 uA
–2 uA
2 uA
2 uA
Output Leakage Current IOL
Output Disable,
VOUT = 0 to VDDQ –2 uA 2 uA
DQ
VT = VDDQ/2
50Ω
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
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Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter Symbol Min. Max. Units Notes
Output High Voltage VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3
Output Low Voltage VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3
Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5
Output Low Voltage VOL2 Vss 0.2 V 4, 6
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ≤ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Operating Currents
Parameter Symbol Test Conditions
-333 -300 -250 -200 -167
Notes
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating Current (x36): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
1050
mA
1075
mA
950
mA
975
mA
850
mA
875
mA
725
mA
750
mA
625
mA
650
mA 2, 3
Operating Current (x18): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
950
mA
975
mA
875
mA
900
mA
775
mA
800
mA
650
mA
675
mA
575
mA
600
mA 2, 3
Operating Current (x9): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
950
mA
975
mA
850
mA
875
mA
750
mA
775
mA
650
mA
675
mA
575
mA
600
mA 2, 3
Operating Current (x8): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
950
mA
975
mA
850
mA
875
mA
750
mA
775
mA
650
mA
675
mA
575
mA
600
mA 2, 3
Standby Current (NOP): DDR ISB1
Device deselected,
IOUT = 0 mA, f = Max,
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
300
mA
310
mA
290
mA
300
mA
270
mA
280
mA
255
mA
265
mA
245
mA
255
mA 2, 4
Notes:
1. Power measured with output pins floating.
2. Minimum cycle, IOUT = 0 mA
3. Operating current is calculated with 50% read cycles and 50% write cycles.
4. Standby Current is only after all pending read and write burst operations are completed.
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AC Electrical Characteristics
Parameter Symbol -333 -300 -250 -200 -167 Units Notes
Min Max Min Max Min Max Min Max Min Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
3.0 5.0 3.3 5.0 4.0 8.4 5.0 8.4 6.0 8.4 ns
tKC Variable tKCVar —0.2 —0.2 —0.2 —0.2 —0.2 ns 5
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.2 —1.32 —1.6 —2.0 —2.4 —ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.2 —1.32 —1.6 —2.0 —2.4 —ns
K to K High
C to C High
tKHKH
tCHCH
1.35 —1.49 —1.8 —2.2 —2.7 —ns
K to K High
C to C High
tKHKH
tCHCH
1.35 —1.49 —1.8 —2.2 —2.7 —ns
K, K Clock High to C, C Clock High tKHCH 00.8 00.8 01.8 0 2.3 02.8 ns
DLL Lock Time tKCLock 1024 —1024 —1024 —1024 —1024 —cycle 6
K Static to DLL reset tKCReset 30 —30 —30 —30 —30 —ns
Output Times
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
—0.45 —0.45 —0.45 —0.45 —0.5 ns 3
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45 —–0.45 —–0.45 —–0.45 —–0.5 —ns 3
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—0.45 —0.45 —0.45 —0.45 —0.5 ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45 —–0.45 —–0.45 —–0.45 —–0.5 —ns
CQ, CQ High Output Valid tCQHQV —0.25 —0.27 —0.30 —0.35 —0.40 ns 7
CQ, CQ High Output Hold tCQHQX –0.25 —–0.27 —–0.30 —–0.35 —–0.40 —ns 7
CQ Phase Distortion tCQHCQH
tCQHCQH
1.10 —1.24 —1.55 —1.95 —2.45 —ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
—0.45 —0.45 —0.45 —0.45 —0.5 ns 3
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
–0.45 —–0.45 —–0.45 —–0.45 —–0.5 —ns 3
Setup Times
Address Input Setup Time tAVKH 0.4 —0.4 —0.5 —0.6 —0.7 —ns
Control Input Setup Time tIVKH 0.4 —0.4 —0.5 —0.6 —0.7 —ns 2
Data Input Setup Time tDVKH 0.28 —0.3 —0.35 —0.4 —0.5 —ns
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Hold Times
Address Input Hold Time tKHAX 0.4 —0.4 —0.5 —0.6 —0.7 —ns
Control Input Hold Time tKHIX 0.4 —0.4 —0.5 —0.6 —0.7 —ns
Data Input Hold Time tKHDX 0.28 —0.3 —0.35 —0.4 —0.5 —ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
3. If C, C are tied high, K, K become the references for C, C timing parameters
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet
parameters reflect tester guard bands and test setup variations.
AC Electrical Characteristics (Continued)
Parameter Symbol -333 -300 -250 -200 -167 Units Notes
Min Max Min Max Min Max Min Max Min Max
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K and K Controlled Read-Write-Read Timing Diagram
Read A Write B NOP Write C Read D Write E NOP
A B C D E
BB+1 B+2 B+3 CC+1 C+2 C+3 EE+1
BB+1 B+2 B+3 CC+1 C+2 C+3 EE+1
AA+1 A+2 A+3 DD+1 D+2
CQHQVKHCQV
KHCQX
CQHQXKHCQV
KHCQX
KHQZ
KHQXKHQV
KHQX1
KHDXDVKH
KHIX
IVKH
KHIX
IVKH
KHIX
IVKH
AVKH
KHKHbar
KLKHKLKH
KHKLKHKL
KHKHKHKH
K
K
Address
R
W
BWx
D
Q
CQ
CQ
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C and C Controlled Read-Write-Read Timing Diagram
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JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS Test Mode Select In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI Test Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO Test Data Out Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
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device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Not Used
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X X X X X 0 0 0 1 1 0 1 1 0 0 1 1
Instruction Register
ID Code Register
Boundary Scan Register
012
0
····
31 30 29 12
0
Bypass Register
TDI TDO
TMS
TCK Test Access Port (TAP) Controller
108
·
10
·
·· ······
Control Signals
·
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Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
110
0
0
1
111
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loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z except CQ.
1
RFU 011 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 30/36 © 2006, GSI Technology
SAMPLE/
PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO. 1
GSI 101 GSI private instruction. 1
RFU 110 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V 1
Test Port Input High Voltage VIHJ 0.6 * VDD VDD +0.3 V 1
TMS, TCK and TDI Input Leakage Current IINHJ –300 1uA 2
TMS, TCK and TDI Input Leakage Current IINLJ –1100 uA 3
TDO Output Leakage Current IOLJ –1 1 uA 4
Test Port Output High Voltage VOHJ VDD – 200 mV —V5, 6
Test Port Output Low Voltage VOLJ —0.4 V5, 7
Test Port Output CMOS High VOHJC VDD – 100 mV —V5, 8
Test Port Output CMOS Low VOLJC —100 mV V5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
JTAG TAP Instruction Set Summary
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 31/36 © 2006, GSI Technology
JTAG Port Timing Diagram
JTAG Port AC Electrical Characteristics
Parameter Symbol Min Max Unit
TCK Cycle Time tTKC 50 —ns
TCK Low to TDO Valid tTKQ —20 ns
TCK High Pulse Width tTKH 20 —ns
TCK Low Pulse Width tTKL 20 —ns
TDI & TMS Set Up Time tTS 10 —ns
TDI & TMS Hold Time tTH 10 —ns
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
DQ
VDDQ/2
50Ω30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKLtTKLtTKHtTKHtTKCtTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 32/36 © 2006, GSI Technology
Package Dimensions—165-Bump FPBGA (Package E)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A1 CORNER TOP VIEW A1 CORNER
BOTTOM VIEW
1.0 1.0
10.0
1.01.0
14.0
15±0.05
17±0.05
A
B
0.20(4x)
Ø0.10
Ø0.25
C
C A B
M
M
Ø0.40~0.60 (165x)
C
SEATING PLANE
0.20 C
0.36~0.46
1.50 MAX.
This package drawing is currently being updated. Please view the correct package drawing at:
http://www.gsitechnology.com/packages.htm.
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 33/36 © 2006, GSI Technology
Ordering Information—GSI SigmaQuad-II SRAM
Org Part Number1Type Package Speed
(MHz) TA2Status3
4M x 8 GS8342D08AE-333 SigmaQuad-II SRAM 165-Pin BGA 333 CPQ
4M x 8 GS8342D08AE-300 SigmaQuad-II SRAM 165-Pin BGA 300 CPQ
4M x 8 GS8342D08AE-250 SigmaQuad-II SRAM 165-Pin BGA 250 CPQ
4M x 8 GS8342D08AE-200 SigmaQuad-II SRAM 165-Pin BGA 200 CPQ
4M x 8 GS8342D08AE-167 SigmaQuad-II SRAM 165-Pin BGA 167 CPQ
4M x 8 GS8342D08AE-333I SigmaQuad-II SRAM 165-Pin BGA 333 IPQ
4M x 8 GS8342D08AE-300I SigmaQuad-II SRAM 165-Pin BGA 300 IPQ
4M x 8 GS8342D08AE-250I SigmaQuad-II SRAM 165-Pin BGA 250 IPQ
4M x 8 GS8342D08AE-200I SigmaQuad-II SRAM 165-Pin BGA 200 IPQ
4M x 8 GS8342D08AE-167I SigmaQuad-II SRAM 165-Pin BGA 167 IPQ
4M x 9 GS8342D09AE-333 SigmaQuad-II SRAM 165-Pin BGA 333 CPQ
4M x 9 GS8342D09AE-300 SigmaQuad-II SRAM 165-Pin BGA 300 CPQ
4M x 9 GS8342D09AE-250 SigmaQuad-II SRAM 165-Pin BGA 250 CPQ
4M x 9 GS8342D09AE-200 SigmaQuad-II SRAM 165-Pin BGA 200 CPQ
4M x 9 GS8342D09AE-167 SigmaQuad-II SRAM 165-Pin BGA 167 CPQ
4M x 9 GS8342D09AE-333I SigmaQuad-II SRAM 165-Pin BGA 333 IPQ
4M x 9 GS8342D09AE-300I SigmaQuad-II SRAM 165-Pin BGA 300 IPQ
4M x 9 GS8342D09AE-250I SigmaQuad-II SRAM 165-Pin BGA 250 IPQ
4M x 9 GS8342D09AE-200I SigmaQuad-II SRAM 165-Pin BGA 200 IPQ
4M x 9 GS8342D09AE-167I SigmaQuad-II SRAM 165-Pin BGA 167 IPQ
2M x 18 GS8342D18AE-333 SigmaQuad-II SRAM 165-Pin BGA 333 CPQ
2M x 18 GS8342D18AE-300 SigmaQuad-II SRAM 165-Pin BGA 300 CPQ
2M x 18 GS8342D18AE-250 SigmaQuad-II SRAM 165-Pin BGA 250 CPQ
2M x 18 GS8342D18AE-200 SigmaQuad-II SRAM 165-Pin BGA 200 CPQ
2M x 18 GS8342D18AE-167 SigmaQuad-II SRAM 165-Pin BGA 167 CPQ
2M x 18 GS8342D18AE-333I SigmaQuad-II SRAM 165-Pin BGA 333 IPQ
2M x 18 GS8342D18AE-300I SigmaQuad-II SRAM 165-Pin BGA 300 IPQ
2M x 18 GS8342D18AE-250I SigmaQuad-II SRAM 165-Pin BGA 250 IPQ
2M x 18 GS8342D18AE-200I SigmaQuad-II SRAM 165-Pin BGA 200 IPQ
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS834x36AE-300T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
3. MP = Mass Production. AS = Pre-Qualification. ES = Engineering Samples. AS = Active Status.
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 34/36 © 2006, GSI Technology
2M x 18 GS8342D18AE-167I SigmaQuad-II SRAM 165-Pin BGA 167 IPQ
1M x 36 GS8342D36AE-333 SigmaQuad-II SRAM 165-Pin BGA 333 CPQ
1M x 36 GS8342D36AE-300 SigmaQuad-II SRAM 165-Pin BGA 300 CPQ
1M x 36 GS8342D36AE-250 SigmaQuad-II SRAM 165-Pin BGA 250 CPQ
1M x 36 GS8342D36AE-200 SigmaQuad-II SRAM 165-Pin BGA 200 CPQ
1M x 36 GS8342D36AE-167 SigmaQuad-II SRAM 165-Pin BGA 167 CPQ
1M x 36 GS8342D36AE-333I SigmaQuad-II SRAM 165-Pin BGA 333 IPQ
1M x 36 GS8342D36AE-300I SigmaQuad-II SRAM 165-Pin BGA 300 IPQ
1M x 36 GS8342D36AE-250I SigmaQuad-II SRAM 165-Pin BGA 250 IPQ
1M x 36 GS8342D36AE-200I SigmaQuad-II SRAM 165-Pin BGA 200 IPQ
1M x 36 GS8342D36AE-167I SigmaQuad-II SRAM 165-Pin BGA 167 IPQ
4M x 8 GS8342D08AGE-333 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 CPQ
4M x 8 GS8342D08AGE-300 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 CPQ
4M x 8 GS8342D08AGE-250 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 CPQ
4M x 8 GS8342D08AGE-200 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 CPQ
4M x 8 GS8342D08AGE-167 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 CPQ
4M x 8 GS8342D08AGE-333I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 IPQ
4M x 8 GS8342D08AGE-300I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 IPQ
4M x 8 GS8342D08AGE-250I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 IPQ
4M x 8 GS8342D08AGE-200I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 IPQ
4M x 8 GS8342D08AGE-167I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 IPQ
4M x 9 GS8342D09AGE-333 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 CPQ
4M x 9 GS8342D09AGE-300 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 CPQ
4M x 9 GS8342D09AGE-250 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 CPQ
4M x 9 GS8342D09AGE-200 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 CPQ
4M x 9 GS8342D09AGE-167 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 CPQ
4M x 9 GS8342D09AGE-333I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 IPQ
4M x 9 GS8342D09AGE-300I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 IPQ
4M x 9 GS8342D09AGE-250I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 IPQ
Ordering Information—GSI SigmaQuad-II SRAM
Org Part Number1Type Package Speed
(MHz) TA2Status3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS834x36AE-300T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
3. MP = Mass Production. AS = Pre-Qualification. ES = Engineering Samples. AS = Active Status.
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 35/36 © 2006, GSI Technology
4M x 9 GS8342D09AGE-200I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 IPQ
4M x 9 GS8342D09AGE-167I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 IPQ
2M x 18 GS8342D18AGE-333 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 CPQ
2M x 18 GS8342D18AGE-300 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 CPQ
2M x 18 GS8342D18AGE-250 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 CPQ
2M x 18 GS8342D18AGE-200 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 CPQ
2M x 18 GS8342D18AGE-167 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 CPQ
2M x 18 GS8342D18AGE-333I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 IPQ
2M x 18 GS8342D18AGE-300I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 IPQ
2M x 18 GS8342D18AGE-250I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 IPQ
2M x 18 GS8342D18AGE-200I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 IPQ
2M x 18 GS8342D18AGE-167I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 IPQ
1M x 36 GS8342D36AGE-333 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 CPQ
1M x 36 GS8342D36AGE-300 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 CPQ
1M x 36 GS8342D36AGE-250 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 CPQ
1M x 36 GS8342D36AGE-200 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 CPQ
1M x 36 GS8342D36AGE-167 SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 CPQ
1M x 36 GS8342D36AGE-333I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 333 IPQ
1M x 36 GS8342D36AGE-300I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 300 IPQ
1M x 36 GS8342D36AGE-250I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 250 IPQ
1M x 36 GS8342D36AGE-200I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 200 IPQ
1M x 36 GS8342D36AGE-167I SigmaQuad-II SRAM RoHS -compliant 165-Pin BGA 167 IPQ
Ordering Information—GSI SigmaQuad-II SRAM
Org Part Number1Type Package Speed
(MHz) TA2Status3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS834x36AE-300T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
3. MP = Mass Production. AS = Pre-Qualification. ES = Engineering Samples. AS = Active Status.
GS8342D08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2007 36/36 © 2006, GSI Technology
Revision History
Rev. Code: Old; New
Types of
Changes
Format or
Content
Revisions
GS8342DxxA_r1 • Creation of new datasheet
GS8342DxxA_r1; GS8342DxxA_r1_01 Content
• Updated MAX tKHKH
• (Rev. 1.01a: Updated Note 4 in HSTL Output Driver DC
Electrical Characteristics table)
GS8342DxxA_r1_01; GS8342DxxA_r1_02 Content • Updated tKHKH, tKHCH in AC Char table
• Added tKHKH and CQ Phase Distortion to AC Char table
GS8342DxxA_r1_02; GS8342DxxA_r1_03 Content • Added Power-up Sequence section
• Added CZ operating currents data
GS8342DxxA_r1_03; GS8342DxxA_r1_04 Content • Changed status to PQ
GS8342DxxA_r1_04; GS8342DxxA_r1_05 Content
• Added VREF note to Pin Description table
• Updated FLXDrive-II Output Driver Impedance Control section
• Removed Preliminary banner due to production status