Microchip 27LV512 512K (64K x 8) Low-Voltage CMOS EPROM FEATURES Wide voltage range 3.0V to 5.5V High speed performance 200ns access time available at 3.0V CMOS Technology for low power consumption 12mA Active current at 3.0V 35mA Active current at 5.5V 100n1A Standby current Factory programming available Auto-insertion-compatible plastic packages Auto ID aids automated programming Separate chip enable and output enable controls High speed Express programming algorithm Organized 64K x 8: JEDEC standard pinouts 28-pin Dual-in-line package 32-pin PLCC package 28-pin SOIC package 28-pin TSOP package Tape and reel Available for the following temperature ranges: Commercial: 0 C to 70 C tIndustrial: -40 C to 85 C DESCRIPTION The Microchip Technology Inc. 27LV512 is a low-volt- age (3.0 volt) CMOS EPROM designed for battery powered applications. The device is organized as a 64K x 8 (64K-Byte) non-volatile memory product. The 27LV512 consumes only 12mA maximum of active current during a 3.0 volt read operation therefore im- proving battery performance. This device is designed for very low-voltage applications where conventional 5.0 volt only EPROMS can not be used. Accessing indi- vidual bytes from an address transition or from power-up (chip enable pin going low) is accomplished in less than 200ns at 3.0 volts. This device allows systems design- ers the ability to use low voltage non-volatile memory with today's low-voltage microprocessors and peripher- als in battery powered applications. A complete family of packages is offered to provide the most flexibility in applications. For surface mount appli- cations, PLCC, SOIC, or TSOP packaging is available. Tape and reel packaging is also available for PLCC or SOIC packages. PIN CONFIGURATIONS Fe Top View mse 28 Veo At2(i2 27D Al4 A713 26] At3 ael4 251] A8 Aas([5 2417] a9 A4C6 230} ait A3L]7 227) OE/Vee a2s8 21 A10 ards 20) CE AOL] 10 19[] 07 oof 18|] 06 o1f12 17005 0213 16[] 04 Vss(] 14 15[] 03 DIP/SOIC 58838 $8582 onoanAnAn OooOoOnoOo RRB HRS SS rao TNOR ene rer HUUUULU UUUCUUO en99948 onnonse sgttegs qgetttid ig TSOP 1993 Microchip Technology Inc. 0S11021C-page 1 8-7327LV512 PIN FUNCTION TABLE ELECTRICAL CHARACTERISTICS . . * Name Function Maximum Ratings Vcc and input voltages w.r.t. VSS.......... -0.6V to +7.25V AO-A15 Address inputs VpP voltage w.r.t. Vss during CE Chip Enable programming -0.6V to +14.0V OE/VpP Output Enable/ Voltage on AQ w.r.t. Vss. .-0.6V to +13.5V Programming Voltage Output voltage w.r.t. Vss .-0.6V to Voc + 1.0V 00-07 Data Output Storage temperature -65 C to 150 C Vcc +3.0V To +5.5V Power Supply Ambient temp. with lied .....-65 C to 125C Vss Ground p. with power applied ..... 65 C to 125 NC No Connection: No internal Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress NU Not Used; No External rating only and functional operation of the device at those or any Connection Is Allowed other conditions above those indicated in the operation listings of this specification is notimplied. Exposure to maximum rating conditions for extended periods may affect device reliability. READ OPERATION Vcc = 3.0V to 5.5V unless otherwise specified DC Characteristics Commercial: Tamb= 0C to 70C Industrial: Tamb= -40C to 85C Parameter Part* Status Symbol Min Max Units | Conditions Input Voltages all | Logic "1" VIH 2.0 Vec+4 Vv Logic "0" VIL -0.5 0.8 Vv input Leakage all tit -10 10 uA | ViIN=0 to Vcc Output Voltages all | Logic "1" VOH 2.4 V_ | loH= -400pA Logic O" VOL 0.45 V_ {| loL=2.1mA Output Leakage all ILo -10 10 HA | VouT= OV to Vcc Input Capacitance all CIN 6 pF | Vin= OV; Tamb = 25 C; f = 1MHz Output Capacitance all CouT 12 pF | Vout= 0V;Tamb= 25 C; f = 1MHz Power Supply Current, | C | TTL input lect 35 @ 5.0V | mA | Vcc = .5V Active 12@3.0V |} mA | f=1MHz,__ | TTL input Icc2 45 @ 5.0V | mA | OE/Vpp= CE = VIL; 12 @ 3.0V | MA | lout = OmA; ViL= -0.1 to 0.8 V; VIH= 2.0 to Vcc; Note (1) Power Supply Current, | C | TTLinput | lcc(sjtTL 1@3.0V | mA Standby | TTL input IcC(S)TTL 2@3.0V | mA] __ all {CMOS input | Iccis)cmos 100 @3.0V| HA | CE = Vcc +0.2V * Parts: C = Commercial Temperature Range; | = Industrial Temperature Range Note: (1) Active current increases 2 mA per MHz up to operating frequency for all temperature ranges. 0811021C-page 2 1993 Microchip Technology Inc. 8-7427LV512 READ OPERATION AC Testing Waveform: = ViH= 2.4V and Vi= 0.45V; VoH= 2.0V VoL =0.8V Input Rise and Fall Times: 10nsec Ambient Temperature: Commercial: Tamb= 0 C to 70C Industrial: Tamb= -40C to 85C Parameter Sym | 27LV512-20 27LV512-25 27LV512-30 Units | Conditions Min Max Min Max Min Max Address to Output Delay | tacc 200 250 300 ns | CE=OE=ViL CE to Output Delay ice 200 250 300 ns | OE=ViL OE to Output Delay toe 90 100 125 ns | CE=ViL CE or OE to O/P High torr | 0 50 0 50 0 50 ns Impedance Output Hold from_ toH 0 0 0 ns Address CE or OE, whichever goes first READ WAVEFORMS VIH Le ~| Address >< lL Address Valid << VIL _ VIH CE _ ViL -- tCE(2) __ Vix OE/VpP Vit - tOFF(1,3) - t tOE(2) | el ton VOH . . Outputs High Z HILT, Valid Output VA. High Z 00-07 Voy AN ZL tacc om Notes: (1) toFF is specified for OE/Vrr or CE, whichever occurs first __ (2) OE may be delayed up to tce - toe after the falling edge of CE without impact on tcE (3) This parameter is sampled and is not 100% tested. 1993 Microchip Technology Inc. DS11021C-page 3 8-7527LV512 PROGRAMMING Ambient Temperature: 25 C +5 C DC Characteristics Vcc = 6.5V + 0.25V, OE/Vpp = VH = 13.0V + 0.25V Parameter Status Symbol | Min Max /|Units| Conditions Input Voltages Logic "1" VIH 2.0 Vec+1 Vv Logic "0" VIL -0.1 0.8 Vv Input Current (all inputs) Iu -10 10 pA | VIN= OV to Vcc Output Voltages Logic "1" VOH 2.4 Vv IOH = -400pA Logic "0" VOL 0.45 Vv loL = 2.1mMA Vcc Current, program & verify leca 35 mA | Note (1) OE/Vver Current,program IPP 25 mA | CE=ViL AQ Product Identification VH 11.5 12.5 Vv Note: (1) Vcc must be applied simultaneously or before the VPP voltage on OE/Ver and removed simultaneously | or after the Ver voltage on OE/Vep. PROGRAMMING AC Testing Waveform: Vin = 2.4V and ViL = 0.45V; VoH= 2.0V; VoL = 0.8V AC Characteristics Ambient Temperature: 25C +5 C for Program, Program Verity Vcc = 6.5V + 0.25V, OE/Ver = VH = 13.0V + 0.25V and Program Inhibit Modes Parameter Symbo! Min Max | Units) Remarks Address Set-Up Time tAS 2 HS Data Set-Up Time tps 2 Bs Data Hold Time {DH 2 ys Address Hold Time tAH 0 us Float Delay (2) {DF 0 130 ns Vcc Set-Up Time tvcs 2 us Program Pulse Width (1) ipw 95 105 us | 100ps typical CE Set-Up Time ICES 2 ps OE Set-Up Time tOES 2 ps OE Hold Time toEH 2 us OE Recovery Time tor 2 us OE/VeP Rise Time During Programming {PRT 50 ns Notes: (1) For Express algorithm, initial programming width tolerance is 100usec + 5%. (2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data is no longer driven (see timing diagram). DS11021C-page 4 1993 Microchip Technology Inc. 8-7627LV512 PROGRAMMING Waveforms (1) Program ot Verify o VIH V a Address x Address Stable Vit RX ae Data __% Data In Stable Data Out Valid _[> VIL X. ~---{ 7 le tps e~| wr be (2) Vcc 5.0V S)e tvcs >} Oy bed tp] 13.0 V (3) OE/Vpp VIL Notes: (1) The input timing reference level is 0.8 V for Vit and 2.0 V for VI. (2) toF and toe are characteristics of the device but must be accommodated by the programmer. (3) Vcc = 6.5 V +0.25 V, Vpp = VH = 13.0 V 0.25 V for express programming algorithm. MODES Read Mode Operation Mode | CE | OEWer | ag | 00-07 (See Timing Diagrams and AC Characteristics) Read Vir | Vit X Dout Read Mode is accessed when Program ViL VH xX DIN Program Verify Vit Vit xX Dout RE win: . Program inhibit Vin | Va X High Z a) the CE pin is low to power up (enable) the chip Standby VIH xX xX High Z __ Output Disable Vi | VIH x High Z b) the OE/VpP pin is low to gate the data to the Identity VIL Vit VH identity Code output pins. X = Don't Care For Read operations, if the addresses are stable, the address access time (tACC) is equal to the delay from CE to output (tce). Data is transferred to the output after a delay (toe) from the falling edge of OE/Vep. 1993 Microchip Technology Inc. DS11021C-page 5 8-7727LV512 Standby Mode The standby mode is defined when the CE pin is high and a program mode is not identified. nable OE/V This multifunction pin eliminates bus contention in microprocessor based systems in which multiple de- vices may drive the bus. The outputs go into a high impedance state when: + the OE/Vep pin is high (VIH). When a VH input is applied to this pin, it supplies the programming voitage (VPP) to the device. Programming Mode The Express algorithm has been developed to improve on the programming throughput times in a production environment. Up to ten 100-microsecond pulses are applied until the byte is verified. A flowchart of the Express algorithm is shown in Figure 1. Programming takes place when: a) Vcc is brought to the proper voltage, b) OE/VpP is brought to the proper VH level, and c) CE line is low. Since the erased state is 1 in the array, programming of 0 is required. The address to be programmed is set via pins AO - A15 and the data to be programmed is presented to pins OO -O7. When data and address are stable, a low going pulse on the CE line programs that location. Verify After the array has been programmed it must be verified to ensure all the bits have been correctly programmed. This mode is entered when all the following conditions are met: a) Vcc is at the proper level, b) the OE/VPP pin is low, and c) the CE line is low. Inhibit When programming multiple devices in parallel with different data, only CE needs to be under separate control to each device. By pulsing the CE line low ona particular device, that device will be programmed; ail other devices with CE held high will not be programmed with the data (although address and data will be avail- able on their input pins). Identity Mode In this mode specific data is output which identifies the manufacturer as Microchip Technology Inc and the device type. This mode is entered when Pin AQ is taken to VH (11.5V to 12.5V). The CE and OE/Vrr lines must be at Vit. AQ is used to access any of the two non- erasable bytes whose data appears on O0 through O7. Pin > Input Output Identity Ao |O/O;O/0;0/0/0/0]H 716/51 4(3/2/1/0];e x Manufacturer] Vit | 0;0/ 1] 0/1])0/0)]1 }29 Device Type*} ViH | 0/0; 0/0/1/1),0 41 JOD * Code subject to change. DS11021C-page 6 1993 Microchip Technology Inc. 8-7827LV512 PROGRAMMING - FIGURE 1 EXPRESS ALGORITHM Conditions: Tamb = 25 C+5C Vcc = 6.5 +0.25V VpP = 13.0 +0.25V ADDR = First Location Vcc = 6.5V Ver = 13.0V X=0 |Program one 100 psec pulse Increment X No Yes / Device Failed Last Address? Yes Increment Address Vcc = VPP = 4.5V, 5.5V All No Device Failed bytes = original data? - 1993 Microchip Technology Inc. 8-79 DS11021C-page 727LV512 SALES AND SUPPORT To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NUMBERS 27LV512 - 25 1/P Package: L Plastic Leaded Chip Carrier P Plastic DIP SO _~Plastic SOIC J Ceramic DIP K Ceramic Leadless Chip Carrier TS Plastic Thin Small Outline (TSOP) = Temperature - 0C to 70 Range: I -40C to8 oc io 85C o Access Time: 20 200 nsec 25 250 nsec 30 300 nsec ee | Device: 27LV512 512K (64K x 8) Low Voltage CMOS EPROM DS11021C-page 8 1993 Microchip Technology inc. 8-80