Preliminary 128M DDR SDRAM K4D263238M 222 / 250 MHz 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Revision 1.1 March 2001 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M Revision History Revision 1.1 (March 5, 2000) * Added K4D263238M-QC40 with VDD&VDDQ=2.8V * Changed VDD/VDDQ of K4D263238M-QC45 from 2.5V to 2.8V. Accordingly, DC current characteristics values have been changed. - Changed CAS latency of K4D263238M-QC45 from CL4 to CL3. * Changed tWPREH of K4D263238M-QC50 from 0.3tCK to 0.25tCK - 2 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M Revision 1.0 (December 13, 2000) * Defined capacitance values * Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK Revision 0.5 (December 8, 2000) * Changed AC input level from Vref + 0.31V to Vref + 0.35V * Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based. * Changed V IN /VOUT /VDDQ in absolute maximum ratings from -1.0V ~3.6V to -0.5V ~ 3.6V. Revision 0.4 (November 29, 2000) - Preliminary * Removed K4D263238M-QC40 * Several AC parameters of K4D263238M-QC45 have been changed - Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns. - Changed tDQSCK & tAC from 0.6ns to 0.7ns - Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK. - Changed tDS/tDH from 0.4ns to 0.45ns. Changed tIS/tIH from 0.9ns to 1.0ns - Corrected tDAL from 5tCK to 6tCK * Several AC parameters of K4D263238M-QC50 have been changed - Changed tQH from tHP-0.6ns to tHP-0.45ns. - Changed tDQSCK & tAC from 0.6ns to 0.7ns - Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK. - Corrected tDAL from 5tCK to 6tCK * Several AC parameters of K4D263238M-QC55 have been changed - Changed tDQSQ from 0.45ns to 0.5ns. Changed tOH from tHP-0.6ns to tHP-0.5ns. - Changed tDQSCK & tAC from 0.6ns to 0.75ns - Changed tDS/tDH from 0.45ns to 0.5ns. Changed tIS/tIH from 1.0ns to 1.1ns - Changed tRC/tRFC from 60.5ns/71.5ns to 66ns/77ns. Changed tRP from 16.5ns to 22ns. - Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK * Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns * Add DC Characteristics value * Define V I H(max) / VIL(min) as a note in Power & DC operating Condition table * Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us. * Changed I IL ,IOL test condition from 0V< V IN <V D D+0.3V to 0V< V IN <V DD. Revision 0.3 (June 8, 2000) * Removed Block Write function Revision 0.2 (April 10, 2000) * Separated tRCD into tRCDRD and tRCDWR - tRCDRD: Row to Column delay for READ - tRCDWR: Row to Column delay at WRITE Revision 0.1 (March 16, 2000) * Define the spec based on Vdd&Vddq=2.5V * Maximum target frequency upto 250MHz@CL4 * Removed Write Interrupt by Read function Revision 0.0 (December 27, 1999) - Target Spec * Defined Target Specification - 3 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL FEATURES * VDD/VDDQ = 2.8V 5% for -40/-45 * Data I/O transactions on both edges of Data strobe * VDD/VDDQ = 2.5V 5% for -50/-55/-60 * DLL aligns DQ and DQS transitions with Clock transition * SSTL_2 compatible inputs/outputs * Edge aligned data & data strobe output * 4 banks operation * Center aligned data & data strobe input * MRS cycle with address key programs * DM for write masking only -. Read latency 3,4 (clock) * Auto & Self refresh -. Burst length (2, 4, 8 and Full page) * 32ms refresh period (4K cycle) -. Burst type (sequential & interleave) * 100pin TQFP package * Full page burst length for sequential burst type only * Maximum clock frequency up to 250MHz * Start address of the full page burst should be even * Maximum data rate up to 500Mbps/pin * All inputs except data & DM are sampled at the positive going edge of the system clock * Differential clock input * No Write Interrupted by Read function ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D263238M-QC40 250MHz 500Mbps/pin K4D263238M-QC45 222MHz 444Mbps/pin K4D263238M-QC50 200MHz 400Mbps/pin K4D263238M-QC55 183MHz 366Mbps/pin K4D263238M-QC60 166MHz 333Mbps/pin Power Supply Interface Package SSTL_2 100 TQFP VDD & VDDQ = 2.8V VDD & VDDQ = 2.5V GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 4 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CK CK CKE MCL A8(AP) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PIN CONFIGURATION (Top View) DQ29 81 50 A7 VSSQ 82 49 A6 DQ30 83 48 A5 DQ31 84 47 A4 VSS 85 46 VSS VDDQ 86 45 A9 N.C 87 44 N.C N.C 88 43 N.C N.C 89 42 N.C N.C 90 41 N.C N.C 91 40 N.C VSSQ 92 39 N.C RFU 93 38 N.C DQS 94 37 A11 VDDQ 95 36 A10 VDD 96 35 VDD DQ0 97 34 A3 DQ1 98 33 A2 VSSQ 99 32 A1 100 31 A0 20 x 14 mm2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQ3 DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 WE CAS RAS CS BA0 BA1 0.65mm pin Pitch VDDQ DQ2 100 Pin TQFP PIN DESCRIPTION CK,CK Differential Clock Input BA 0 , BA 1 Bank Select Address CKE Clock Enable A 0 ~A 11 Address Input CS Chip Select D Q0 ~ DQ3 1 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe VS S Ground WE Write Enable V DDQ Power for DQ s DQS Data Strobe V SSQ Ground for DQ s DMi Data Mask MCL Must Connect Low RFU Reserved for Future Use - 5 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function The differential system clock Input. CK, CK *1 Input CKE Input All of the inputs are sampled on the rising edge of the clock except D Q s and DM s that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the com- CS Input mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input CAS Input WE Input DQS Input/Output Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data input and output are synchronized with both edge of DQS. Data In mask. Data In is masked by DM Latency=0 when DM is high DM 0 ~ DM 3 Input in burst write. DM 0 for DQ 0 ~ DQ 7, DM 1 for DQ 8 ~ DQ 15, DM 2 for D Q1 6 ~ DQ 23, DM 3 for DQ24 ~ DQ 31. DQ 0 ~ DQ 31 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA 0, BA 1 Input Selects which bank is to be active. A 0 ~ A 11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA 0 ~ RA 1 1, Column addresses : CA 0 ~ CA7. Column address CA 8 is used for auto precharge. V DD/V SS Power Supply Power and ground for the input buffers and core logic. V DDQ/V SSQ Power Supply V REF Power Supply Reference voltage for inputs, used for SSTL interface. MCL Must Connect Low Must connect Low Isolated power supply and ground for the output buffers to provide improved noise immunity. *1 : The timing reference point for the differential clocking is the cross point of CK and CK . For any applications using the single ended clocking, apply V REF to CK pin. - 6 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank) 32 Intput Buffer I/O Control CK, CK Data Input Register LWE LDMi Serial to parallel Bank Select 64 1Mx32 32 Output Buffer 1Mx32 64 2-bit prefetch S ense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 1Mx32 x32 DQi 1Mx32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length LRAS LCBR Strobe G en. Programming Register LCKE Data Strobe DLL LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 7 - DMi Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M FUNCTIONAL DESCRIPTION * Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high. 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. * 1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 5 6 7 8 9 10 11 t RP 2 Clock min. 2 Clock min. tRP Command precharge ALL Banks EMRS MRS DLL Reset precharge 1st Auto ALL Banks Refresh 12 - 8 - 14 15 16 tRFC t RFC 200 Clock min. Inputs must be stable for 200 us 13 4 2nd Auto Refresh 3 17 18 19 2 Clock min. Mode Register Set Any Command 2 1 0 CK CK Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A 0 ~ A 11 and BA 0, BA 1 in the same cycle as CS, RAS, CAS and W E going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A 3, CAS latency(read latency from column address) uses A 4 ~ A 6. A7 is used for test mode. A 8 is used for DLL reset. A 7, A 8, BA 0 and BA 1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA 1 BA 0 RFU 0 A1 1 A1 0 A9 RFU A8 A7 DLL TM A6 A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Address Bus Mode Register Burst Type Test Mode DLL A8 DLL Reset A3 Type A7 mode 0 Sequential 1 Interleave 0 No 0 Normal 1 Yes 1 Test Burst Length CAS Latency BA 0 A2 A1 A0 Burst Type An ~ A0 A6 A5 A4 Latency Sequential Interleave 0 MRS 0 0 0 Reserved 0 0 0 Reserve Reserve 1 EMRS 0 0 1 Reserved 0 0 1 2 2 1 0 4 4 * RFU(Reserved for future use) should stay "0" during MRS cycle. 0 1 0 Reserved 0 0 1 1 3 0 1 1 8 8 1 0 0 4 1 0 0 Reserve Reserve 1 0 1 Reserved 1 0 1 Reserve Reserve 1 1 0 Reserved 1 1 0 Reserve Reserve Reserved 1 1 1 Full page Reserve 1 1 1 MRS Cycle 0 1 2 3 4 5 6 7 8 CK, CK Command NOP Precharge All Banks NOP NOP MRS tRP NOP Any Command NOP NOP tMRD=2 t CK *1: MRS can be issued only at all banks precharge state. *2: Minimum t RP is required to issue MRS command. - 9 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and W E going low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA 1 BA 0 RFU 1 BA 0 A1 1 A 10 A9 A8 A7 RFU A6 A5 D.I.C An ~ A0 A6 A1 0 MRS 0 1 1 EMRS 1 1 A4 A3 A2 RFU Output Driver Impedance Control A1 A0 D.I.C DLL A0 Address Bus Extended Mode Register DLL Enable 60% of full drive strength 0 Enable Matched impedance 30% of full drive strength 1 Disable Weak * RFU(Reserved for future use) should stay "0" during EMRS cycle. Figure 7. Extend Mode Register set - 10 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit V IN, V OUT -0.5 ~ 3.6 V Voltage on V DD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on V DD supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature T STG -55 ~ +150 C Power dissipation PD 2.0 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS=0V, T A =0 to 65C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage V DD 2.375 2.50 2.625 V 1,7 Output Supply voltage V DDQ 2.375 2.50 2.625 V 1,7 Device Supply voltage V DD 2.66 2.8 2.94 V 1,8 Output Supply voltage V DDQ 2.66 2.8 2.94 V 1,8 Reference voltage V REF 0.49*V DDQ - 0.51*V DDQ V 2 Termination voltage Vtt V REF-0.04 V REF V REF+0.04 V 3 Input logic high voltage V IH V REF+0.15 - V DDQ +0.30 V 4 Input logic low voltage V IL -0.30 - V REF-0.15 V 5 Output logic high voltage VO H Vtt+0.76 - - V IO H=-15.2mA Output logic low voltage V OL - - Vtt-0.76 V IOL =+15.2mA Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Note : 1. Under all conditions V DDQ must be less than or equal to VDD. 2. V REF is expected to equal 0.50*V DDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V REF may not exceed + 2% of the DC value. Thus, from 0.50*V DDQ , VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. V tt of the transmitting device must track V REF of the receiving device. 4. V IH (max.)= V DDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. V IL (min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V V IN V DD is acceptable. For all other pins that are not under test V IN=0V. 7. For -50/-55/-60, V DD/ V DDQ =2.5 V + 5% 8. For -40/-45, V DD/V DDQ = 2.8V + 5% - 11 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T A=0 to 65C) Parameter Version Symbol Test Condition Unit Note -40 -45 -50 -55 -60 330 310 260 260 260 Operating Current (One Bank Active) ICC1 Burst Lenth=2 t RC t RC(min) IOL=0mA, tCC= tCC(min) Precharge Standby Current in Power-down mode ICC2 P CKE V IL (max), tCC = tCC(min) Precharge Standby Current in Non Power-down mode ICC2 N CKE V IH(min), CS V IH(min), tCC= tCC(min). Active Standby Current power-down mode ICC3 P CKE V IL (max), t CC= tCC (min) Active Standby Current in in Non Power-down mode ICC3 N CKE VIH(min), CS VIH(min), tCC= tCC(min) . 200 190 160 150 140 mA Operating Current ( Burst Mode) ICC4 IOL =0mA , tCC= t C C(min), Page Burst, All Banks activated. 710 660 550 500 460 mA Refresh Current ICC5 tRC tRFC (min) 400 380 330 320 320 mA Self Refresh Current ICC6 CKE 0.2V 90 160 80 155 135 130 105 4 1 mA 125 95 5 mA mA mA 2 mA Note: 1. Measured with outputs open. 2. Refresh period is 32ms. AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V SS =0V, V DD/ VDDQ =2.5V+ 5%/2.8V+ 5% Parameter *Note 3 , TA =0 to 65C) Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ V IH V REF +0.35 - - V Input Low (Logic 0) Voltage; DQ V IL - - V REF -0.35 V Clock Input Differential Voltage; CK and CK V ID 0.7 - V DDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK V IX 0.5*VDDQ-0.2 - 0.5*V DDQ +0.2 V 2 Note : 1. V I D is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of V IX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same 3. For -40/-45, V DD/V DDQ = 2.8 V + 5%, For -50/-55/-60, V DD/V DDQ = 2.5 V + 5% - 12 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M AC OPERATING TEST CONDITIONS ( V DD/ V DDQ=2.5V + 5%/2.8V+ 5%*Note , TA= 0 to 65C ) Parameter Value Unit Input reference voltage for CK(for single ended) 0.50*V DDQ V 1.5 V CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(V IH /V IL) 1.0 V/ns V REF +0.35/V REF -0.35 V V REF V V tt V Input timing measurement reference level Output timing measurement reference level Output load condition Note See Fig.1 Note : -40/-45, VDD/V DDQ = 2.8 V + 5%, For -50/-55/-60, V DD/V DDQ = 2.5 V + 5% V tt=0.5*V DDQ R T=50 Output Z0=50 V REF =0.5*VDDQ C LOAD =30pF (Fig. 1) Output Load Circuit CAPACITANCE (V DD =2.5V, T A = 25C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK ) C IN1 1.0 5.0 pF Input capacitance(A 0 ~A10 , BA0 ~BA1 ) C IN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) C IN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ 0~ D Q31) C OUT 1.0 6.0 pF Input capacitance(DM0 ~ DM3) C IN4 1.0 6.0 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between V DD and V SS C DC1 0.1 + 0.01 uF Decoupling Capacitance between V DDQ and V SSQ C DC2 0.1 + 0.01 uF Note : 1. V DD and V DDQ pins are separated each other. All V DD pins are connected in chip. All VDDQ pins are connected in chip. 2. V SS and V SSQ pins are separated each other All V SS pins are connected in chip. All V SSQ pins are connected in chip. - 13 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M AC CHARACTERISTICS Parameter Symbol -40 -45 -50 -55 -60 Unit Note Max Min Max Min Max Min Max Min Max 7 4.5 7 5.0 7 5.5 7 6.0 7 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns - +0.4 - +0.45 - +0.45 - +0.5 - +0.5 ns 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.8 1.2 0.8 1.2 0.8 1.2 0.75 1.25 0.75 1.25 tCK 0 - 0 - 0 - 0 - 0 - ns 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK tIS 0.9 - 1.0 - 1.0 - 1.1 - 1.1 - ns 0.9 - 1.0 - 1.0 - 1.1 - 1.1 - ns 0.4 - 0.45 - 0.45 - 0.5 - 0.5 - ns DQ and DM hold time to DQS tI H tDS tDH 0.4 - 0.45 - 0.45 - 0.5 - 0.5 - ns Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns 1 Data output hold time from DQS tQ H tHP-0.4 - tHP-0.45 - tHP-0.45 - tHP-0.5 - tHP-0.5 - ns 1 CL=3 CK cycle time CL=4 tCK tCH CK low level width tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in tDQSS DQS-In setup time tWPRES DQS-in hold time tWPREH DQS write postamble tWPST DQS-In high level width tDQSH DQS-In low level width tDQSL CK high level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS Min 4.5 4.0 ns ns 1 Simplified Timing @ BL=2, CL=3 tCH tCL tCK 0 1 2 3 4 5 6 7 8 CK, CK tIS CS tIH tDQSCK tDQSS DQS tRPRE tRPST t WPRES tDQSQ tDQSH tWPST tWPREH Hi-Z tDS tDH tAC DQ Da1 Db0 Da2 Db1 Hi-Z DM WRITEB COMMAND READA - 14 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL3, BL2) tHP 0 1 2 3 4 5 CK, CK CS DQS tDQSQ(max) tQH tDQSQ(max) Da0 DQ COMMAND Da1 READA - 15 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M AC CHARACTERISTICS (I) Parameter Row cycle time Symbol tRC tRFC Row active time tRAS RAS to CAS delay for Read tRCDRD RAS to CAS delay for Write tRCDWR Row precharge time tRP Row active to Row active tRRD Last data in to Row precharge tWR Refresh row cycle time -40 -45 -50 -55 -60 Unit Min Max Min Max Min Max Min Max Min Max 15 - 13 - 12 - 12 - 10 - tCK 17 - 15 - 14 - 14 - 12 - tCK 10 100K 9 100K 8 100K 8 100K 7 100K 5 - 4 - 4 - 4 - 3 - tCK tCK 3 5 2 4 3 - 2 - 2 - tCK 4 2 - 3 2 - 2 - tCK tCK 2 4 2 - Note 2 - 2 - 2 - 2 - 2 - tCK 1 tCDLR 2 - 2 - 2 - 2 - 2 - tCK 1 tCCD tMRD 1 2 - 1 2 - 1 2 - 1 2 - 1 Mode register set cycle time 2 - tCK tCK Auto precharge write recovery + Precharge tDAL 7 - 6 - 6 - 6 - 5 - tCK Exit self refresh to read com- tXSR 200 - 200 - 200 - 200 - 200 - tCK Power down exit time tPDEX tREF 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - ns us Last data in to Read command Col. address to Col. address Refresh interval time 7.8 7.8 7.8 7.8 7.8 Note :1 For normal write operation, even numbers of Din are to be written inside DRAM - 16 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M (Unit : Number of Clock) AC CHARACTERISTICS (II) K4D263238M-QC40 Frequency 250MHz ( 4.0ns ) 222MHz ( 4.5ns ) 200MHz ( 5.0ns ) 183MHz ( 5.5ns ) 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 4 3 3 3 3 3 tRC 15 13 12 12 10 9 tRFC 17 15 14 14 12 11 tRAS 10 9 8 8 7 6 tRCDRD 5 4 4 4 3 3 tRCDWR 3 2 2 2 2 2 tRP 5 4 4 4 3 3 tRRD 3 2 2 2 2 2 Unit K4D263238M-QC45 Frequency 222MHz ( 4.5ns ) 200MHz ( 5.0ns ) 183MHz ( 5.5ns ) 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 3 3 3 3 3 tRC 13 12 12 10 9 tRFC 15 14 14 12 11 tRAS 9 8 8 7 6 tRCDRD 4 4 4 3 3 tRCDWR 2 2 2 2 2 tRP 4 4 4 3 3 tRRD 2 2 2 2 2 Unit K4D263238M-QC50 Frequency 200MHz ( 5.0ns ) 183MHz ( 5.5ns ) 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 3 3 3 3 tRC 12 12 10 9 tRFC 14 14 12 11 tRAS 8 8 7 6 tRCDRD 4 4 3 3 tRCDWR 2 2 2 2 tRP 4 4 3 3 tRRD 2 2 2 2 Unit K4D263238M-QC55 Frequency 183MHz ( 5.5ns ) 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 3 3 3 tRC 12 10 9 tRFC 14 12 11 tRAS 8 7 6 tRCDRD 4 3 3 tRCDWR 2 2 2 tRP 4 3 3 tRRD 2 2 2 Unit K4D263238M-QC60 Frequency 166MHz ( 6.0ns ) 143MHz ( 7.0ns ) Cas Latency 3 3 tRC 10 9 tRFC 12 11 tRAS 7 6 tRCDRD 3 3 tRCDWR 2 2 tRP 3 3 tRRD 2 2 Unit - 17 - tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M Simplified Timing(2) @ BL=4, CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CK, CK BA[1:0] BAa A8/AP RaRa ADDR (A0~A7, A9~,A11) Ra BAa BAa Ca BAa BAb Ra Rb Ra Rb BAa BAb Ca Cb WE DQS Da0 Da1 Da2 Da3 DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM ACTIVEA WRITEA COMMAND PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRP tRC Normal Write Burst (@ BL=4) tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 18 - Rev. 1.1 (Mar. 2001) Preliminary 128M DDR SDRAM K4D263238M PACKAGE DIMENSIONS (TQFP) Dimensions in Millimeters 0 ~ 7 17.20 0.20 14.00 0.10 #100 #1 0.20 20.00 0.10 0.575 23.20 0.825 0.30 0 . 0 8 0.13 MAX 0.65 0.09~0.20 1.00 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 0.20 - 19 - Rev. 1.1 (Mar. 2001)