CD4047BMS - Harris Semiconductor

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

SEMICONDUCTOR

CD4047BMS

CMOS Low-Power

Monostable/Astable Multivibrator

Description

CD4047BMS consists of a gatable astable multivibrator with logic tech-

niques incorporated to permit positive or negative edge triggered

monostable multivibrator action with retriggering and external counting

options.

Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE,

RETRIGGER, and EXTERNAL RESET . Buf fered outputs are Q,Q, and

OSCILLAT OR. In all modes of operation, an external capacitor must be

connected between C-Timing and RC-Common terminals, and an

external resistor must be connected between the R-Timing and RC-

Common terminals.

Astable operation is enabled by a high level on the AST ABLE input or a

low level on theASTABLE input, or both. The period of the square wave

at the Q and Q Outputs in this mode of operation is a function of the

external components employed. “True” input pulses on the ASTABLE

input or “Complement” pulses on theASTABLE input allow the circuit to

be used as a gatable multivibrator . The OSCILLAT OR output period will

be half of the Q terminal output in the astable mode. However, a 50%

duty cycle is not guaranteed at this output.

The CD4047BMS triggers in the monostable mode when a positive

going edge occurs on the +TRIGGER input while the -TRIGGER is held

low . Input pulses may be of any duration relative to the output pulse.

If retrigger capability is desired, the RETRIGGER input is pulsed. The

retriggerable mode of operation is limited to positive going edge. The

CD4047BMS will retrigger as long as the RETRIGGER input is high,

with or without transitions (See Figure 31)

An external countdown option can be implemented by coupling “Q” to

an external “N” counter and resetting the counter with trigger pulse. The

counter output pulse is fed back to the ASTABLE input and has a dura-

tion equal to N times the period of the multivibrator.

A high level on the EXTERNAL RESET input assures no output pulse

during an “ON” power condition. This input can also be activated to ter-

minate the output pulse at any time. For monostable operation, when-

ever VDD is applied, an internal power on reset circuit will clock the Q

output low within one output period (tM).

The CD4047BMS is supplied in these 14-lead outline packages:

Pinout

CD4047BMS

TOP VIEW

Braze Seal DIP H4Q

Frit Seal DIP H1B

Ceramic Flatpack H3W

R-C COMMON

ASTABLE

-TRIGGER

VSS

VDD

OSC OUT

RETRIGGER

EXT. RESET

+TRIGGER

Features

• High Voltage Type (20V Rating)

• Low Power Consumption: Special CMOS Oscillator

Conﬁguration

• Monostable (One-Shot) or Astable (Free-Running)

Operation

• True and Complemented Buffered Outputs

• Only One External R and C Required

• Buffered Inputs

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Monostable Multivibrator Features

• Positive or Negative Edge Trigger

• Output Pulse Width Independent of Trigger Pulse

Duration

• Retriggerable Option for Pulse Width Expansion

• Internal Power-On Reset Circuit

• Long Pulse Widths Possible Using Small RC Compo-

nents by Means of External Counter Provision

• Fast Recovery Time Essentially Independent of Pulse

Width

• Pulse-Width Accuracy Maintained at Duty Cycles

Approaching 100%

Astable Multivibrator Features

• Free-Running or Gatable Operating Modes

• 50% Duty Cycle

• Oscillator Output Available

• Good Astable Frequency Stability: Frequency Deviation:

-=±2% + 0.03%/oC at 100kHz

-=±0.5% + 0.015%/oC at 10kHz (Circuits “Trimmed”

to Frequency VDD = 10V ± 10%

Applications

Digital equipment where low power dissipation and/or high noise

immunity are primary design requirements

• Envelope Detection

• Frequency Multiplication

• Frequency Division

• Frequency Discriminators

• Timing Circuits

• Time Delay Applications

December 1992

File Number 3313

7-898

Speciﬁcations CD4047BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . . θja θjc

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K). . . . . . 500mW

For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-2µA

2 +125oC - 200 µA

VDD = 18V, VIN = VDD or GND 3 -55oC-2µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA

2 +125oC -1000 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

2 +125oC - 1000 nA

VDD = 18V 3 -55oC - 100 nA

Input Leakage Curent

(Pin 3) IIL VDD = 24V, VIN = 11V or GND 1 +25oC -300 - nA

2 +125oC -10 - µA

Input Leakage Current

(Pin 3) IIH VDD = 26V, VIN = 13V or GND 1 +25oC - 300 nA

2 +125oC-10µA

Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV

Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V

Output Current (Sink)

Q, Q, OSC Out IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA

Output Current (Sink)

Q, Q, OSC Out IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA

Output Current (Sink)

Q, Q, OSC Out IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA

Output Current (Source)

Q, Q, OSC Out IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA

Output Current (Source)

Q, Q, OSC Out IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA

Output Current (Source)

Q, Q, OSC Out IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA

Output Current (Source)

Q, Q, OSC Out IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA

Output Current (Sink) IOL5RC VDD = 5V, VOUT = 0.4V 1 +25oC 0.78 - mA

Output Current (Sink) IOL10RC VDD = 10V, VOUT = 0.5V 1 +25oC 2.0 - mA

Output Current (Sink) IOL15RC VDD = 15V, VOUT = 1.5V 1 +25oC 5.2 - mA

Output Current (Source) IOH5RC VDD = 5V, VOUT = 4.6V 1 +25oC - -0.78 mA

Output Current (Source) IOH10RC VDD = 10V, VOUT = 9.5V 1 +25oC - -2 mA

Output Current (Source) IOH15RC VDD = 15V, VOUT = 13.5V 1 +25oC - -5.2 mA

N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V

7-899

Speciﬁcations CD4047BMS

P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V

Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD/2 VOL <

VDD/2 V

VDD = 20V, VIN = VDD or GND 7 +25oC

VDD = 18V, VIN = VDD or GND 8A +125oC

VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

Input Voltage High

(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

Input Voltage Low

(Note 2) VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V

Input Voltage High

(Note 2) VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V

NOTES:

1. All voltages referenced to device GND, 100% testing being implemented

2. Go/No Go test with limits applied to inputs.

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max..

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL (NOTES 1, 2)

CONDITIONS GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Propagation Delay

Astable, Astable to OSC TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns

10, 11 +125oC, -55oC - 540 ns

Propagation Delay

Trigger to Q, Q TPHL3

TPLH3 VDD = 5V, VIN = VDD or GND 9 +25oC - 1000 ns

10, 11 +125oC, -55oC - 1350 ns

Propagation Delay

(Note 2)

Astable orAstable to Q , Q

TPLH2

TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 700 ns

10, 11 +125oC, -55oC - 945 ns

Propagation Delay

(Note 2)

Retrigger to Q, Q

TPHL4

TPLH4 VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns

10, 11 +125oC, -55oC - 810 ns

Propagation Delay

(Note 2)

Reset to Q, Q

TPLH5

TPLH5 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns

10, 11 +125oC, -55oC - 675 ns

Transition Time TTHL

TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

NOTES:

1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

7-900

Speciﬁcations CD4047BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA

+125oC-30µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

+125oC-60µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

+125oC - 120 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC-50mV

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC-50mV

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC4.95 - V

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC9.95 - V

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

-55oC-3V

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

-55oC+7 - V

Propagation Delay

Astable, Astable to OSC TPLH1 VDD = 10V 1, 2, 3 +25oC - 200 ns

VDD = 15V 1, 2, 3 +25oC - 160 ns

Propagation Delay

Astable orAstable to Q , Q TPLH2

TPHL2 VDD = 10V 1, 2, 3 +25oC - 350 ns

VDD = 15V 1, 2, 3 +25oC - 250 ns

Propagation Delay

Trigger to Q, Q TPHL3

TPLH3 VDD = 10V 1, 2, 3 +25oC - 450 ns

VDD = 15V 1, 2, 3 +25oC - 300 ns

Propagation Delay

Retrigger to Q, Q TPHL4

TPLH4 VDD = 10V 1, 2, 3 +25oC - 300 ns

VDD = 15V 1, 2, 3 +25oC - 200 ns

Propagation Delay

Reset to Q, Q TPLH5

TPLH5 VDD = 10V 1, 2, 3 +25oC - 200 ns

VDD = 15V 1, 2, 3 +25oC - 140 ns

Transition Time TTHL

TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

7-901

Speciﬁcations CD4047BMS

Q or Q Deviation from

50% Duty Factor QD VDD = 5V 1, 2, 3 +25oC-±1%

VDD = 10V 1, 2, 3 +25oC-±1%

VDD = 15V 1, 2, 3 +25oC-±0.5 %

Minimum Pulse Width

+ Trigger

- Trigger

TW VDD = 5V 1, 2, 3 +25oC - 400 ns

VDD = 10V 1, 2, 3 +25oC - 160 ns

VDD = 15V 1, 2, 3 +25oC - 100 ns

Minimum Pulse Width

Reset TW VDD = 5V 1, 2, 3 +25oC - 200 ns

VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 60 ns

Minimum Retrigger Pulse

Width TW VDD = 5V 1, 2, 3 +25oC - 600 ns

VDD = 10V 1, 2, 3 +25oC - 230 ns

VDD = 15V 1, 2, 3 +25oC - 150 ns

Input Capacitance CIN Any Input 1, 2 +25oC - 7.7 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA

N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V

N Threshold Voltage

Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V

P Threshold Voltage

Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

VDD/2 VOL <

VDD/2 V

VDD = 3V, VIN = VDD or GND

Propagation Delay Time TPHL

TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

+25oC

Limit

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-1 IDD ± 0.2µA

Output Current (Sink) IOL5 ± 20% x Pre-Test Reading

Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

7-902

Speciﬁcations CD4047BMS

TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUP MIL-STD-883

METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Final Test 100% 5004 2, 3, 8A, 8B, 10, 11

Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS MIL-STD-883

METHOD

TEST READ AND RECORD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION OPEN GROUND VDD 9V ± -0.5V OSCILLATOR

50kHz 25kHz

Static Burn-In 1

Note 1 1, 2, 10, 11, 13 3-9, 12 14

Static Burn-In 2

Note 1 1, 2, 10, 11, 13 7 3-6, 8, 9, 12, 14

Dynamic Burn-

In Note 1 - 7, 9, 12 4, 5, 14 1, 2, 10, 11, 13 6, 8 3

Irradiation

Note 2 1, 2, 10, 11, 13 7 3-6, 8, 9, 12, 14

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V ± 0.5V

7-903

CD4047BMS

TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS

In all cases External resistor between terminals 2 and 3 (Note 1)

External capacitor between terminals 1 and 3 (Note 1)

FUNCTION

TERMINAL CONNECTIONS OUTPUT PULSE

FROM OUTPUT PERIOD OR PULSE

WIDTHTO VDD TO VSS INPUT TO

ASTABLE MULTIVIBRATOR

Free Running 4, 5, 6, 14 7, 8, 9, 12 - 10, 11, 13 TA (10, 11) = 4.40 RC

True Gating 4, 6, 14 7, 8, 9, 12 5 10, 11, 13 TA (13) = 2.20 RC (Note 2)

Complement Gating 6, 14 5, 7, 8, 9, 12 4 10, 11, 13

MONOSTABLE MULTIVIBRATOR

Positive Edge Trigger 4, 14 5, 6, 7, 9, 12 8 10, 11 tM (10, 11) = 2.48 RC

Negative Edge Trigger 4, 8, 14 5, 7, 9, 12 6 10, 11

Retriggerable 4, 14 5, 6, 7, 9 8, 12 10, 11

External Countdown (Note 3) 14 5, 6, 7, 8, 9, 12 - 10, 11

NOTES:

1. See text.

2. First positive1/2 cycle pulse width = 2.48 RC. See note follow Monostable Mode Design Information.

3. Input Pulse to Reset of External Counting Chip External Counting Chip Output to Terminal 4.

Logic Diagrams

FIGURE 1. CD4047BMS LOGIC BLOCK DIAGRAM

OSCILLATOR OUT

LOW POWER

ASTABLE

MULTIVIBRATOR

FREQUENCY

DIVIDER (÷2)

ASTABLE

GATE

CONTROL

MONOSTABLE

CONTROL

RETRIGGER

CONTROL

213 R-TIMINGC-TIMING

COMMON

-TRIGGER

ASTABLE

+TRIGGER

RETRIGGER

EXTERNAL

RESET

ASTABLE

7-904

CD4047BMS

FIGURE 2. CD4047BMS LOGIC DIAGRAM

(a)

(b)

FIGURE 3. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS FF1 AND FF3 (a) AND FOR FLIP-FLOPS FF2 AND FF4 (b)

Logic Diagrams

(Continued)

FF1

R1 R2

VDD

FF3

R1 R2

FF2

FF4

VSS

OSC

OUT

2RTC

CTC

3RC

COMMON

RETRIGGER *VDD

VDD

VSS

EXTERNAL

RESET

-TRIGGER

+TRIGGER

ASTABLE

VDD

VSS

VDD

VSS

INPUTS PROTECTED

BY CMOS

PROTECTION

NETWORK

*SPECIAL

RC COMMON

PROTECTION

NETWORK

CAUTION: Terminal 3 is more sensitive

to static electrical discharge. Extra

handling precautions are recommended.

CL p

R2 R1

R2R1

CL DQ

FF1, FF3

R2R1

FF2, FF4

7-905

CD4047BMS

Typical Performance Characteristics

FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 6. TYP. OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE8. TYP. PROPAGATION DELA Y TIME AS A FUNCTION OF

LOAD CAPACIT ANCE (ASTABLE,ASTABLE TO Q, Q) FIGURE 9. TYP. PROPAGATION DELAY TIME AS A FUNCTION

OF LOAD CAP ACIT ANCE (+ OR - TRIGGER TO Q,Q)

10V

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

0 5 10 15

DRAIN-TO-SOURCE VOLT AGE (VDS) (V)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

10V

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOL TAGE (VGS) = 15V

0 5 10 15

7.5

5.0

2.5

10.0

12.5

15.0

DRAIN-TO-SOURCE VOLT AGE (VDS) (V)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

-10V

-15V

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOL TAGE (VGS) = -5V

-2.5

-5

-7.5

DRAIN-TO-SOURCE VOLT AGE (VDS) (V)

-10

-12.5

-15

0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

-10V

-15V

AMBIENT TEMPERATURE (TA) = +25oC0

-2.5

-5

-7.5

DRAIN-TO-SOURCE VOLT AGE (VDS) (V) 0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOL TAGE (VGS) = -5V

SUPPLY VOLTAGE (VDD) = 5V

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

100

0LOAD CAPACITANCE (CL) (pF)

15V

10V

AMBIENT TEMPERATURE (TA) = +25oC

200

300

400

20 40 60 80 100

SUPPLY VOLTAGE (VDD) = 5V

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

200

0LOAD CAPACITANCE (CL) (pF)

15V

10V

AMBIENT TEMPERATURE (TA) = +25oC

20 40 60 80 100

400

600

7-906

CD4047BMS

FIGURE 10. TYP. TRANSITION TIME AS A FUNCTION OF LOAD

CAPACITANCE FIGURE 11. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD

ACCURACY vs SUPPLY VOLTAGE

FIGURE 12. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD

ACCURACY vs SUPPLY VOLTAGE FIGURE 13. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD

ACCURACY vs SUPPLY VOLTAGE

FIGURE 14. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD

ACCURACY vs AMBIENT TEMPERATURE (ULTRA

LOW FREQ.)

FIGURE 15. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD

ACCURACY vs AMBIENT TEMPERATURE (LOW

FREQ.)

Typical Performance Characteristics

(Continued)

AMBIENT TEMPERATURE (TA) = +25oC

LOAD CAPACITANCE (CL) (pF)

0 40 60 80 10020

100

150

200

SUPPLY VOL TAGE (VDD) = 5V

10V

15V

TRANSITION TIME (fTHL, fTLH) (ns)

-1

-2

-3

-4

PERIOD ACCURACY (%)

0 2 4 6 810 1214161820

SUPPLY VOLTAGE (VDD) (V)

AMBIENT TEMPERATURE (TA) = +25oC

CX = 1µF

10kΩ

10MΩ

1MΩ AND 100kΩ

10kΩ

10MΩ

RX = 1MΩ AND

100kΩ

-1

-2

-3

-4

PERIOD ACCURACY (%)

0 2 4 6 810 1214161820

SUPPLY VOLTAGE (VDD) (V)

AMBIENT TEMPERATURE (TA) = +25oC

CX = 0.01µF

10kΩ

1MΩ

10kΩ

100kΩ

RX = 1MΩ

10MΩ

100kΩ

-1

-2

-3

-4

PERIOD ACCURACY (%)

0 2 4 6 810 1214161820

SUPPLY VOLTAGE (VDD) (V)

AMBIENT TEMPERATURE (TA) = +25oC

CX = 1000pF

10kΩ

1MΩ AND

10kΩ

100kΩ

RX = 1MΩ AND

10kΩ10kΩ10MΩ

PERIOD ACCURACY (%)

-55 -15 25 65 105 145

AMBIENT TEMPERATURE (TA) (oC)

-3

-2

-1

1CX = 1µF

RX = 1MΩ

SUPPLY VOLTAGE (VDD) = 5V 5V

10V, 15V

PERIOD ACCURACY (%)

-55

AMBIENT TEMPERATURE (TA) (oC)

2CX = 0.1µF

RX = 1MΩ

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

-1

-2 -15 25 65 105 145

15V

10V

7-907

CD4047BMS

FIGURE 16. TY P. A S TABLE OSCILLATOR OR Q, Q PERIOD

ACCURACY vs AMBIENT TEMPERATURE (MEDIUM

FREQ.)

FIGURE 17. TY P. A S TABLE OSCILLATOR OR Q,Q PERIOD

ACCURACY vs AMBIENT TEMPERATURE (HIGH

FREQ.)

FIGURE18. TYPICAL ASTABLE OSCILLATOR OR Q,Q PERIOD

ACCURACY vs AMBIENT TEMPERATURE FIGURE 19. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs

SUPPLY VOLTAGE

FIGURE 20. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs

SUPPLY VOLTAGE FIGURE 21. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs

SUPPLY VOLTAGE

Typical Performance Characteristics

(Continued)

PERIOD ACCURACY (%)

-55 -15 25 65 105 145

AMBIENT TEMPERATURE (TA) (oC)

2CX = 0.01µF

RX = 100kΩSUPPLY VOLTAGE (VDD) = 5V, 10V

5V AND 10V

-1

-2

15V

PERIOD ACCURACY (%)

-55 -15 25 65 105 145

AMBIENT TEMPERATURE (TA) (oC)

12 CX = 1000pF

RX = 10kΩ

10V AND 15V

10V, 15V

-2

-4

SUPPLY VOLTAGE (VDD) = 5V

-35 -5 45 85 125

PERIOD ACCURACY (%)

-55 -15 25 65 105 145

AMBIENT TEMPERATURE (TA) (oC)

-10

RX = 10kΩ

SUPPLY VOLTAGE (VDD) = 5V

100pF

0.001µF

0.01µF, 0.1µF, 1µF

0.001µF

CX = 100pF

0.01µF, 0.1µF, 1µF

AMBIENT TEMPERATURE (TA) = +25oC

CX = 1µF

OUTPUT PULSE-WIDTH VARIATION (%)

-8

-6

-4

-2

0 5 10 15 20 25

SUPPLY VOLTAGE (VDD) (V)

1kΩ

10kΩ

RX = 100kΩ, 1MΩ, 10MΩ

100kΩ

1kΩ

10kΩ, 1MΩ AND 10MΩ

AMBIENT TEMPERATURE (TA) = +25oC

CX = 0.1µF

OUTPUT PULSE-WIDTH VARIATION (%)

-8

-6

-4

-2

0 5 10 15 20 25

SUPPLY VOLTAGE (VDD) (V)

10MΩ10kΩ, 100kΩ, 1MΩ AND 10MΩ

RX = 10kΩ, 100kΩ, 1MΩ

AMBIENT TEMPERATURE (TA) = +25oC

CX = 1000pF

OUTPUT PULSE-WIDTH VARIATION (%)

-8

-6

-4

-2

0 5 10 15 20 25

SUPPLY VOLTAGE (VDD) (V)

RX = 1MΩ AND 10Ω

100kΩ

10kΩ

7-908

CD4047BMS

FIGURE 22. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs

AMBIENT TEMPERATURE FIGURE 23. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs

AMBIENT TEMPERATURE

FIGURE 24. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs

AMBIENT TEMPERATURE FIGURE 25. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs

AMBIENT TEMPERATURE

FIGURE 26. TYPICAL POWER DISSIPATION vs OUTPUT

FREQUENCY (VDD = 5V) FIGURE 27. TYPICAL POWER DISSIPATION vs OUTPUT

FREQUENCY (VDD = 10V)

Typical Performance Characteristics

(Continued)

RX = 100kΩ

SUPPLY VOLTAGE (VDD) = 5V

0.001µF

OUTPUT PULSE-WIDTH VARIATION (%)

-8

-6

-4

-2

-55 -15 25 65 105 145

AMBIENT TEMPERATURE (TA) (oC)

0.01µF

0.1µF

0.001µF

0.01µF

0.1µF

-35 5 45 85 125

RX = 100kΩ

SUPPLY VOLTAGE (VDD) = 10V OR 15V

OUTPUT PULSE-WIDTH VARIATION (%)

-12-50 AMBIENT TEMPERATURE (TA) (oC)

-35 -15 5 25 45 65 85 105 125 145

-10

-8

-6

-4

-2

0.1µF AND 0.001µF

CX = 100pF

0.01µF

0.1µF, 0.01µF

0.001µF

100pF

-55 -15 25 65 105 145

AMBIENT TEMPERATURE (TA) (oC)

-35 5 45 85 125

CX = 1000pF

SUPPLY VOLTAGE (VDD) = 5V OR 10V

OUTPUT PULSE-WIDTH VARIATION (%)

-12

-10

-8

-6

-4

-2

100kΩ

RX = 1MΩ

10kΩ

10MΩ

1MΩ

10kΩ

100kΩ

CX = 1000pF

SUPPLY VOLTAGE (VDD) = 15V

OUTPUT PULSE-WIDTH VARIATION (%)

-12-50 AMBIENT TEMPERATURE (TA) (oC)

-35 -15 5 25 45 65 85 105 125 145

-10

-8

-6

-4

-2

10MΩ

10kΩ

RX = 1MΩ100kΩ

1MΩ

10MΩ

10kΩ

100kΩ

ASTABLE MODE

SUPPLY VOLTAGE (VDD) = 5V

POWER DISSIPATION (PD) (µW)

105

104

103

102

101

100

10-1 100101102103104105106

Q OR Q FREQUENCY (F) (Hz)

C = 0.1µFC = 0.01µFC =1000pF

C =100pF

C =10pF

ASTABLE MODE

SUPPLY VOLTAGE (VDD) = 10V

POWER DISSIPATION (PD) (µW)

105

104

103

102

101

10-1 100101102103104105106

Q OR Q FREQUENCY (F) (Hz)

C = 0.1µFC = 0.01µF

C =1000pF

C =100pF

C =10pF

106

7-909

CD4047BMS

FIGURE 28. TYPICAL POWER DISSIPATION vs OUTPUT FREQUENCY (VDD = 15V)

Typical Performance Characteristics

(Continued)

ASTABLE MODE

SUPPLY VOLTAGE (VDD) = 15V

POWER DISSIPATION (PD) (µW)

105

104

103

102

10-1 100101102103104105106

Q OR Q FREQUENCY (F) (Hz)

C = 0.1µF

C = 0.01µFC =1000pF

C =100pF

C =10pF

Astable Mode Design Information

Unit-to-Unit Transfer Voltage Variations

The following analysis presents variations from unit to unit as

a function of transfer voltage (VTR) shift (33%-67% VDD) for

free running (astable) operation.

FIGURE 29. ASTABLE MODE WAVEFORMS

thus if is used, the variation will be +5%, -0%

due to variations in transfer voltage.

Variations Due to VDD and Temperature Changes

In addition to variations from unit to unit, the astable period

varies with VDD and temperature, Typical variations are pre-

sented in graphical form in Figures 11 to 18 with 10V as ref-

erence for voltage variations curves and +25oC as reference

for temperature variations curves.

t1 = -RC In VTR ;

VDD + VTR

typically, t1 = 1.1RC

t2 = -RC In VDD - VTR ;

2VDD - VTR

typically, t2 = 1.1RC

tA = 2(t1 + t2)

= -2RC In (VTR)(VDD - VTR)

(VDD + VTR)(2VDD - VTR)

Typ:

Min:

Max:

VTR = 0.5VDD

VTR = 0.33VDD

VTR = 0.67VDD

tA = 4.40RC

tA = 4.62RC

t1 t2 t1 t2

tA/2 tA/2

TERMINAL 13

TERMINAL 10

tA = 4.40RC

Monostable Mode Design Information

The following analysis presents variations from unit to unit as a

function of transfer voltage (VTR) shift (33% - 67% VDD) for

one shot (monostable) operation.

FIGURE 30. MONOSTABLE WAVEFORMS

thus if is used, the variation will be +9.3%,

-0% due to variations in transfer voltage.

NOTES:

1. In the astable mode, the ﬁrst positive half cycle has a duration of

tM; succeeding durations are tA/s.

2. In addition to variations from unit to unit, the monostable pulse

width varies with VDD and temperature. These variations are

presented in graphical form in Figures 19 to 26 with 10V as ref-

erence for voltage variation curves and +25oC as reference for

temperature variation curves.

t1´ = -RC In VTR ;

2VDD

typically, t1´ = 1.38RC

tM = (t1´ + t2)

tM = -RC In (VTR)(VDD - VTR)

(2VDD - VTR)(2VDD)

where tM = Monostable mode pulse width.

Values for tM are as follows:

Typ:

Min:

Max:

VTR = 0.5VDD

VTR = 0.33VDD

VTR = 0.67VDD

tM = 2.48RC

tM = 2.71RC

tM = 2.48RC

t1´ t2 t1´ t2

tM tM

TERMINAL 13

TERMINAL 10

TERMINAL 8

tM = 2.48RC

7-910

CD4047BMS

Retrigger Mode Operation

The CD4047BMS can be used in the retrigger mode to extend

the output pulse duration, or to compare the frequency of an

input signal with that of the internal oscillator. In the retrigger

mode the input pulse is applied to terminal 12, and the output is

taken from terminal 10 or 11. As shown in Figure 31 normal

monostable action is obtained when one retrigger pulse is

applied. Extended pulse duration is obtained when more than

one pulse is applied.

For two input pulses, tRE = t1´ + t1 + 2t2. For more than two

pulses, the output pulse width is an integral number of time peri-

ods, with the ﬁrst time period being t1´ + t2, typically , 2.48RC, and

all subsequent time periods being t1 + t2, typically, 2.2RC.

External Counter Option

T ime tM can be extended by any amount with the use of external

counting circuitry. Advantages include digitally controlled pulse

duration, small timing capacitors for long time periods, and

extremely fast recovery time. A typical implementation is shown

in Figure 32. The pulse duration at the output is

text = (N - 1) (t A) + (tM + t A/2)

where text = pulse duration of the circuitry, and N is the number

of counts used.

FIGURE 32. IMPLEMENT ATION OF EXTERNAL COUNTER OPTION

Timing Component Limitations

The capacitor used in the circuit should be non polarized and

have low leakage (i.e. the parallel resistance of the capacitor

should be at least an order of magnitude greater than the exter-

nal resistor used). There is no upper or lower limit for either R or

C value to maintain oscillation.

AST

CD4047BMS CD4017BMS

CL OUT

INPUT

PULSE

OPTIONAL

BUFFER

TEXT

However, in consideration of accuracy, C must be much larger

than the inherent stray capacitance in the system (unless this

capacitance can be measured and taken into account). R must

be much larger than the CMOS “ON” resistance in series with

it, which typically is hundreds of Ω. In addition, with very large

values of R, some short term instability with respect to time may

be noted.

The recommended values for these components to maintain

agreement with previously calculated formulas without trimming

should be:

C≥ 100pF, up to any practical value, for astable modes;

C≥ 1000pF, up to any practical value for monostable modes.

10kΩ≤ R ≤ 1MΩ

Power Consumption

In the standby mode (Monostable or Astable), power dissipa-

tion will be a function of leakage current in the circuit, as shown

in the static electrical characteristics. For dynamic operation,

the power needed to charge the external timing capacitor C is

given by the following formula:

Astable Mode:

P = 2CV2f. (Output at terminal No. 13)

P = 4CV2f. (Output at terminal Nos. 10 and 11)

Monostable Mode:

(Output at terminal Nos. 10 to 11)

The circuit is designed so that most of the total power is con-

sumed in the external components. In practice, the lower the

values of frequency and voltage used, the closer the actual

power dissipation will be to the calculated value.

Because the power dissipation does not depend on R, a

design for minimum power dissipation would be a small value

of C. The value of R would depend on the desired period

(within the limitations discussed above). See Figures 26, 27,

and 28 for typical power consumption in astable mode.

P = (2.9CV2) (Duty Cycle)

FIGURE 31. RETRIGGER MODE WAVEFORMS

t1´ t2

tRE

+TRIGGER &

t1´ t2 t1´ t2

tRE

t1´ t2 t1´ t2t1´ t2 t1´ t2

tRE

t1´ t2 t1´ t2t1´ t2

tRE

RETRIGGER

TERMINALS

8 & 12

OSC OUTPUT

TERMINAL 13

Q OUTPUT

TERMINAL 10

7-911

CD4047BMS

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are

derived from the basic inch dimensions as indicated.

Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ−14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches