©2005 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
RFG70N06, RFP70N06, RF1S70N06,
RF1S70N06SM
70A, 60V, 0.014 Ohm, N-Channel Power
MOSFETs
These are N -Channel powe r MO SFET s m an u fac tur ed u sin g
the MegaFET proc es s. This proces s, which uses fea ture
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, result ing in outstanding performance.
They were designed for use in applications such as
s witchi ng regulato rs, s witch ing con v erters , motor driv ers and
rela y driv ers. These tr ansistors ca n be operated direc tly from
integrated circuits.
Formerly developmental type TA78440.
Features
• 70A, 60V
•r
DS(on) = 0.014Ω
• Temperature Compensated PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve (Single Pulse)
•175
oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC STYL E T O- 247
JEDEC TO-220AB
JEDEC TO-263AB
JEDEC TO-262AA
Ordering Information
PART NUMBER PACKAGE BRAND
RFG70N06 TO-247 RFG70N06
RFP70N06 TO-220AB RFP70N06
RF1S70N06 TO-262AA F1S70N06
RF1S70N06SM TO-263AB F1S70N06
NOTE: When ordering use the ent ire part number . Add the suffix 9A to
obtain the TO-263AB variant in ta pe and reel , e . g. RF1S 70N06SM9A.
G
D
S
DRAIN
(BOTTOM
SIDE METAL)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
Data Sheet February 2005
©2005 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG70N06, RFP70N06
RF1S70N06, RF1S70N06SM UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 60 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .VDGR 60 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulse d D ra in Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I DM 70
Re fe r to Pe ak Cu rr en t Curv e A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Singl e P u l se Avalanch e R a t in g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve A
Power Dis sipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
1.0 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL
P ackage Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: St resses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a stress on ly rating and operatio n of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 60 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Zero Gate Voltage Drain Current IDSS VDS = 60V, VGS = 0V - - 1 µA
VDS = 0.8 x Rated BVDSS, TC = 150oC--25µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 70A, VGS = 10V (Figure 9) - - 0.014 Ω
Turn-On Time t(ON) VDD = 30V, ID ≈ 70A, RL = 0.43Ω,
VGS = 10V, RGS = 2.5Ω
(Figure 13)
- - 190 ns
Turn-On Delay Time td(ON) -10- ns
Rise Time tr- 137 - ns
Turn-Off Delay Time td(OFF) -32- ns
Fall Ti me tf-24- ns
Turn-Off Time t(OFF) - - 73 ns
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 48V, ID = 70A,
RL = 0.68Ω
Ig(REF) = 2.2mA
(Figure 13)
- 120 156 nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 65 85 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 5.0 6.5 nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1 MHz
(Figure 12) - 2250 - pF
Output Capacitance COSS - 792 - pF
Reverse Transfer Capacitance CRSS - 206 - pF
Thermal Resistance, Junction to Case RθJC --1.0
oC/W
Thermal Resistance, Junction to Ambient RθJA TO-220 and TO-263 - - 62 oC/W
TO-247 - - 30 oC/W
Sour ce to Drain Diode Specificatio ns
PARAMETER SYMBOL TEST CONDITIONS MIN TYP M AX UNITS
Source to Drain Diode Voltage VSD ISD = 70A - 1.5 V
Reverse Recovery Time trr ISD = 70A, dISD/dt = 100A/µs - 52 ns
NOTES:
2. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%.
3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
©2005 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
Typical Performance Curves TC = 25oC, Unless Otherwise Specified
FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRE NT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
30
10
025 50 75 100 125 150
50
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
70
175
40
20
60
80
1
0.1
0.01
10-5 10-4 10-3 10-2 10-1 100101
t, RECTANGULAR PULSE DURATION (s)
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
0.02
0.05
0.1
0.2
0.5
THERMAL IMPEDANCE
ZθJC, NORMALIZED
PDM
t1t2
SINGLE PULSE
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
100
10
1
110 100
OPE RATIO N IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
100µs
1ms
10ms
500
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
t, PULSE WIDTH (s)
5010-5 10-4 10-3 10-2 10-1 100101
100
IDM, PEAK CURRENT (A)
1000
FOR TEMPERATURES
ABO VE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
II
25 175 TC
–
150
-----------------------
=
TC = 25oC
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
©2005 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERIS TICS FIGURE 9. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD V OLTA GE vs
JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves TC = 25oC, Unless Otherwise Specified (Continued)
0.01 0.1
100
300
10
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R) ln [(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
110 0
80
0123 5
120
160
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 7V
VGS = 10V
200
4
VGS = 5V
VGS = 4.5V
VGS = 20V VGS = 8V
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 6V
0468102
0
40
80
120
IDS(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
160 -55oC25oC
200
175oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
0
0.5
1
1.5
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC) 200
2
2.5
VGS = 10V, ID = 70A
PULSE DURATION = 250µs
ON RESISTANCE
DUTY CYCLE = 0.5% MAX
-80 -40 0 40 80 120 160
0
0.5
1.0
1.5
2.0
NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATU RE (oC) 200
VGS = VDS, ID = 250µA2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
200
ID = 250µA
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
©2005 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZE D SWITCHING W A V EFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY W AVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. SWITCHING WAVEFORMS
Typical Performance Curves TC = 25oC, Unless Otherwise Specified (Continued)
5000
1000
00 5 10 15 20 25
C, CAPACITANCE (pF)
4000
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
3000
2000
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
60
45
30
15
0
10
7.5
5
2.5
0
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
IG(REF)
IG(ACT)
20 IG(REF)
IG(ACT)
80
t, TIME (µs)
RL = 0.86Ω
IG(REF) = 2.2mA
VGS = 10V
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
VDD = BVDSS
VDD = BVDSS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
©2005 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
©2005 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
PSPICE Electrical Model
.SUBCKT RFG70N06 2 1 3 ; rev 3/20/92
CA 12 8 5.56e-9
CB 15 14 5.30e-9
CIN 6 8 2.63e-9
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 65.18
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 3.10e-9
LSOURCE 3 7 1.82e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 4.66e-3
RLDRAIN 2 5 10
RGATE 9 20 1.21
RLGATE 1 9 31
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.92e-3
RLSOURCE 3 7 18.2
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.605
.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8)
.MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5)
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (V TO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7)
.MODEL RDSMOD RES (T C1 = 2.23e-3 TC2 = 6.56e-6)
.MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 V OFF= -6.35)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 V OFF= -8.35)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Te mpe rature Options; written by William J. Hepp and C. Frank Wheatle y.
1
GATE
LGATE RGATE
EVTO
+
12 13
814
13
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
RIN CIN
MOS1
MOS2
DBREAK
EBREAK
DBODY
LDRAIN DRAIN
RSOURCE
LSOURCESOURCE
RBREAK
RVTO
VBAT
IT
VTO
ESG
DPLCAP
6
10 5
16
21
11
17
18
8
14
73
17 18
19
2
++
+
+
+
+
20
RDRAIN
ESCL
RSCL1RSCL2
51
50
+
9
RLGATE
RLDRAIN
RLSOURCE
5
51
18
8
6
8
-
-
-
-
5
8
6
8
--
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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ISOPLANAR™
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MicroPak™
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OCX™
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OPTOLOGIC
OPTOPLANAR™
PACMAN™
FAST
FASTr™
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FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
i-Lo™
ImpliedDisconnect™
Rev. I15
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CROSSVOLT™
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QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
µSerDes™
SILENT SWITCHER
SMART ST ART™
SPM™
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SuperSOT™-3
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SuperSOT™-8
SyncFET™
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TINYOPTO™
TruTranslation™
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UniFET™
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Across the board. Around the world.™
The Power Franchise
Programmable Active Droop™
