Dual 3 MHz, 800 mA Buck
Regulators with Two 300 mA LDOs
Data Sheet
ADP5037
Rev. B
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FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 800 mA buck regulators and two 300 mA LDOs
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±1.8%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
The ADP5037 combines two high performance buck regulators
and two low dropout (LDO) regulators in a small, 24-lead 4 mm ×
4 mm LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low and the
load is above a predefined threshold, the buck regulators
operate in PWM mode. When the load current falls below a
predefined threshold, the regulator operates in power save
mode (PSM), improving the light-load efficiency.
The two bucks operate out of phase to reduce the input capaci-
tor requirement. The low quiescent current, low dropout voltage,
and wide input voltage range of the ADP5037 LDOs extend the
battery life of portable devices. The ADP5037 LDOs maintain
power supply rejection greater than 60 dB for frequencies as
high as 10 kHz while operating with a low headroom voltage.
Regulators in the ADP5037 are activated though dedicated
enable pins. The default output voltages can be externally set in
the adjustable version or factory programmable to a wide range
of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
AGND
VIN3
EN2
EN3
EN4
VIN4
EN1
VIN1
PWM
PSM/PWM
2.3V TO
5.5V SW1
FB1
R2
R1
VOUT1
PGND1
MODE
C5
10µF
V
OUT1
AT
800mA
V
OUT2
AT
800mA
V
OUT3
AT
300mA
V
OUT4
AT
300mA
L1 1µ H
EN1
BUCK1
MODE
C3
1µF
C2
4.7µF
C1
4.7µF
AVIN
C
AVIN
0.1µF
C4
1µF
VIN2
EN2
BUCK2
MODE
1.7V TO
5.5V
ON
OFF
ON
OFF
EN3 LDO1
(ANALOG)
ADP5037
HOUSEKEEPING
SW2
FB2
R4
R3
VOUT2
PGND2 C6
10µF
L2 1µ H
FB3
R6
R5
VOUT3
C7
1µF
FB4
R8
R7
VOUT4
C8
1µF
EN4 LDO2
(DIGITAL)
09887-001
Figure 1.
ADP5037 Data Sheet
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
General Specifications ................................................................. 3
BUCK1 and BUCK2 Specifications ........................................... 4
LDO1 and LDO2 Specifications ................................................. 4
Input and Output Capacitor, Recommended Specifications .. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Power Management Unit ........................................................... 15
BUCK1 and BUCK2 .................................................................. 17
LDO1 and LDO2 ........................................................................ 18
Applications Information .............................................................. 19
Buck External Component Selection ....................................... 19
LDO External Component Selection....................................... 21
Power Dissipation and Thermal Considerations ....................... 22
Buck Regulator Power Dissipation .......................................... 22
Junction Temperature ................................................................ 23
PCB Layout Guidelines .................................................................. 24
Typical Application Schematics .................................................... 25
Bill of Materials ............................................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
8/12—Rev. A to Rev. B
Changes to Regulator Accuracy, Features Section ....................... 1
Changes to Output Voltage Accuracy, Table 2 and Voltage
Feedback, Table 2 .............................................................................. 4
Changes to Output Voltage Accuracy, Table 3 and Voltage
Feedback, Table 3 .............................................................................. 4
Changes to Figure 6, Figure 7, and Figure 8.................................. 8
Changes to Figure 9 to Figure 14 .................................................... 9
Changes to Figure 30 and Figure 31 ............................................. 12
Changes to Figure 34 and Figure 38 Caption ............................. 13
Changes to Undervoltage Lockout Section ................................. 16
Moved Power Dissipation and Thermal Considerations
Section .............................................................................................. 22
Changes to Buck Regulator Power Dissipation Section ............ 22
Changes to PCB Layout Guidelines Section ............................... 24
Changes to Ordering Guide .......................................................... 27
1/12—Rev. 0 to Rev. A
Changes to Features Section and Figure 1 ..................................... 1
Changes to Table 2 and Table 3........................................................ 4
Changes to Table 4 ............................................................................. 5
Changes to Table 5 ............................................................................. 6
Changes to Table 7 ............................................................................. 7
Changes to Figure 34 ...................................................................... 13
Changes to Buck Regulator Power Dissipation Section ............ 15
Changes to Undervoltage Lockout Section ................................. 18
Changes to LDO1 and LDO2 Section ......................................... 20
Changes to Table 9 .......................................................................... 22
Changes to Figure 52 and Figure 53 ............................................ 25
Changes to Ordering Guide .......................................................... 27
8/11—Revision 0: Initial Version
Data Sheet ADP5037
Rev. B | Page 3 of 28
SPECIFICATIONS
GENERAL SPECIFICATIONS
VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; VIN3 = VIN4 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA =
25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE V
AVIN
, V
IN1
, V
IN2
2.3 5.5 V
THERMAL SHUTDOWN
Threshold TS
SD
T
J
rising 150 °C
Hysteresis TS
SD-HYS
20 °C
START-UP TIME
1
BUCK1, LDO1, LDO2 t
START1
250 µs
BUCK2 t
START2
300 µs
EN1, EN2, EN3, EN4, MODE INPUTS
Input Logic High V
IH
1.1 V
Input Logic Low V
IL
0.4 V
Input Leakage Current V
I-LEAKAGE
0.05 1 µA
INPUT CURRENT
All Channels Enabled I
STBY-NOSW
No load, no buck switching 108 175 µA
All Channels Disabled I
SHUTDOWN
T
J
= −40°C to +85°C 0.3 1 µA
VIN1 UNDERVOLTAGE LOCKOUT
High UVLO Input Voltage Rising UVLO
VIN1RISE
3.9 V
High UVLO Input Voltage Falling
UVLOV IN1FAL L
3.1
V
Low UVLO Input Voltage Rising UVLO
VIN1RISE
2.275 V
Low UVLO Input Voltage Falling UVLO
VIN1FA L L
1.95 V
1 Start-up time is defined as the time from EN1 = EN2 = EN3 = EN4 from 0 V to VAVIN to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up
times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
ADP5037 Data Sheet
Rev. B | Page 4 of 28
BUCK1 AND BUCK2 SPECIFICATIONS
VAVI N = VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.1
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Accuracy ΔVOUT1/VOUT1,
ΔV
OUT2
/V
OUT2
PWM mode; ILOAD1 = ILOAD2 = 0 mA −1.8 +1.8 %
Line Regulation (∆VOUT1/VOUT1)/∆VIN1,
(∆V
OUT2
/V
OUT2
)/∆V
IN2
PWM mode −0.05 %/V
Load Regulation (∆VOUT1/VOUT1)/∆IOUT1,
(∆V
OUT2
/V
OUT2
)/∆I
OUT2
ILOAD = 0 mA to 800 mA, PWM mode −0.1 %/A
VOLTAGE FEEDBACK
VFB1, VFB2
Models with adjustable outputs
0.491
0.5
0.509
V
OPERATING SUPPLY CURRENT MODE = ground
BUCK1 Only IIN ILOAD1 = 0 mA, device not switching, all other
channels disabled
44 μA
BUCK2 Only IIN ILOAD2 = 0 mA, device not switching, all other
channels disabled
55 μA
BUCK1 and BUCK2 IIN ILOAD1 = ILOAD2 = 0 mA, device not switching,
LDO channels disabled
67 μA
PSM CURRENT THRESHOLD I
PSM
PSM to PWM operation 100 mA
SW CHARACTERISTICS
SW On Resistance R
NFET
V
IN1
= V
IN2
= 3.6 V 155 240 mΩ
R
PFET
V
IN1
= V
IN2
= 3.6 V 205 310 mΩ
R
NFET
V
IN1
= V
IN2
= 5.5 V 137 204 mΩ
R
PFET
V
IN1
= V
IN2
= 5.5 V 162 243 mΩ
Current Limit
ILIMIT1, ILIMIT2
pFET switch peak current limit
1200
1550
1900
mA
ACTIVE PULL-DOWN R
PDWN-B
Channel disabled 75 Ω
OSCILLATOR FREQUENCY f
SW
2.5 3.0 3.5 MHz
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO1 AND LDO2 SPECIFICATIONS
VIN3 = (VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, VIN4 = (VOUT4 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT =
1 µF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE V
IN3
, V
IN4
1.7 5.5 V
OPERATING SUPPLY CURRENT
Bias Current per LDO
2
I
VIN3BIAS
/I
VIN4BIAS
I
OUT3
= I
OUT4
= 0 µA 10 30 µA
I
OUT3
= I
OUT4
= 10 mA 60 100 µA
I
OUT3
= I
OUT4
= 300 mA 165 245 µA
Total System Input Current IIN Includes all current into AVIN, VIN1, VIN2, VIN3,
and VIN4
LDO1 or LDO2 Only I
OUT3
= I
OUT4
= 0 µA, all other channels disabled 53 µA
LDO1 and LDO2 Only I
OUT3
= I
OUT4
= 0 µA, buck channels disabled 74 µA
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
ΔVOUT3/VOUT3,
ΔV
OUT4
/V
OUT4
100 µA < IOUT3 < 300 mA, 100 µA < IOUT4 < 300 mA −1.8 +1.8 %
Line Regulation (∆VOUT3/VOUT3)/∆VIN3,
(∆V
OUT4
/V
OUT4
)/∆V
IN4
IOUT3 = IOUT4 = 1 mA −0.03 +0.03 %/V
Load Regulation3
(∆V
OUT3
/V
OUT3
)/∆I
OUT3
,
(∆V
OUT4
/V
OUT4
)/∆I
OUT4
I
OUT3
= I
OUT4
= 1 mA to 300 mA
0.001
0.003
%/mA
Data Sheet ADP5037
Rev. B | Page 5 of 28
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VOLTAGE FEEDBACK VFB3, VFB4
0.491 0.5 0.509 V
DROPOUT VOLTAGE4
VDROPOUT
VOUT3 = VOUT4 = 5.2 V, IOUT3 = IOUT4 = 300 mA
50
mV
V
OUT3
= V
OUT4
= 3.3 V, I
OUT3
= I
OUT4
= 300 mA 75 140 mV
V
OUT3
= V
OUT4
= 2.5 V, I
OUT3
= I
OUT4
= 300 mA 100 mV
V
OUT3
= V
OUT4
= 1.8 V, I
OUT3
= I
OUT4
= 300 mA 180 mV
CURRENT-LIMIT THRESHOLD
5
I
LIMIT3
, I
LIMIT4
335 600 mA
ACTIVE PULL-DOWN R
PDWN-L
Channel disabled 600 Ω
OUTPUT NOISE
Regulator LDO1 NOISE
LDO1
10 Hz to 100 kHz, V
IN3
= 5 V, V
OUT3
= 2.8 V 100 µV rms
Regulator LDO2 NOISE
LDO2
10 Hz to 100 kHz, V
IN4
= 5 V, V
OUT4
= 1.2 V 60 µV rms
POWER SUPPLY REJECTION
RATIO
PSRR
Regulator LDO1 10 kHz, V
IN3
= 3.3 V, V
OUT3
= 2.8 V, I
OUT3
= 1 mA 60 dB
100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA
62
dB
1 MHz, V
IN3
= 3.3 V, V
OUT3
= 2.8 V, I
OUT3
= 1 mA 63 dB
Regulator LDO2 10 kHz, V
IN4
= 1.8 V, V
OUT4
= 1.2 V, I
OUT4
= 1 mA 54 dB
100 kHz, V
IN4
= 1.8 V, V
OUT4
= 1.2 V, I
OUT4
= 1 mA 57 dB
1 MHz, V
IN4
= 1.8 V, V
OUT4
= 1.2 V, I
OUT4
= 1 mA 64 dB
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 This is the input current into VIN3/VIN4, which is not delivered to the output load.
3 Based on an endpoint calculation using 1 mA and 300 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.7 V.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified.
Table 4.
Parameter Symbol Min Typ Max Unit
NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS
BUCK1, BUCK2 Input Capacitor Ratings C
MIN1
, C
MIN2
4.7 40 µF
BUCK1, BUCK2 Output Capacitor Ratings
CMIN1, CMIN2
10
40
µF
LDO
1
Input and Output Capacitor Ratings C
MIN3
, C
MIN4
1.0 µF
CAPACITOR ESR R
ESR
0.001 1 Ω
1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.
ADP5037 Data Sheet
Rev. B | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVIN to AGND −0.3 V to +6 V
VIN1, VIN2 to AVIN
−0.3 V to +0.3 V
PGND1, PGND2 to AGND −0.3 V to +0.3 V
VIN3, VIN4, VOUT1, VOUT2, FB1, FB2,
FB3, FB4, EN1, EN2, EN3, EN4,
MODE to AGND
−0.3 V to (AVIN + 0.3 V)
VOUT3 to AGND
−0.3 V to (VIN3 + 0.3 V)
VOUT4 to AGND −0.3 V to (VIN4 + 0.3 V)
SW1 to PGND1 −0.3 V to (VIN1 + 0.3 V)
SW2 to PGND2 −0.3 V to (VIN2 + 0.3 V)
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
24-Lead, 0.5 mm pitch LFCSP 35 3 °C/W
ESD CAUTION
Data Sheet ADP5037
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. NC = NO CO NNE C T. DO NOT CONNE CT TO THIS PIN.
2. IT IS RECOMME NDE D THAT THE EXPOSED PAD
BE SOLDERED TO T HE GROUND P LANE.
1
2
3
4
5
6
15
16
17
18
14
13
7
8
9
11
12
10 21
22
23
24
20
19
ADP5037
TOP VIEW
(No t t o Scal e)
VOUT4
FB3
VOUT3
VIN3
EN3
VIN4
AGND
AVIN
VIN1
SW1
PGND1
MODE
FB4
EN4
VIN2
SW2
PGND2
NC
EN1
FB1
VOUT1
VOUT2
FB2
EN2
09887-003
Figure 2. Pin Configuration—View from the Top of the Die
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 FB4 LDO2 Feedback Input. For device models with adjustable output voltage, connect this pin to the middle of the
LDO2 resistor divider. For device models with fixed output voltage, connect this pin to the top of the capacitor on
VOUT4.
2 EN4 LDO2 Enable Pin. High level turns on this regulator, and low level turns it off.
3 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN.
4 SW2 BUCK2 Switching Node.
5 PGND2 Dedicated Power Ground for BUCK2.
6 NC No Connect. Leave this pin unconnected.
7 EN2 BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off.
8 FB2 BUCK2 Feedback Input. For device models with adjustable output voltage, connect this pin to the middle of the
BUCK2 resistor divider. For device models with fixed output voltage, leave this pin unconnected.
9 VOUT2 BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2.
10
VOUT1
BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1.
11 FB1 BUCK1 Feedback Input. For device models with adjustable output voltage, connect this pin to the middle of the
BUCK1 resistor divider. For device models with fixed output voltage, leave this pin unconnected.
12 EN1 BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off.
13 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation.
14 PGND1 Dedicated Power Ground for BUCK1.
15 SW1 BUCK1 Switching Node.
16 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN.
17 AVIN Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2.
18 AGND Analog Ground.
19 FB3 LDO1 Feedback Input. For device models with adjustable output voltage, connect this pin to the middle of the
LDO1 resistor divider. For device models with fixed output voltage, connect this pin to the top of the capacitor on
VOUT3.
20 VOUT3 LDO1 Output Voltage.
21 VIN3 LDO1 Input Supply (1.7 V to 5.5 V).
22 EN3 LDO1 Enable Pin. High level turns on this regulator, and low level turns it off.
23 VIN4 LDO2 Input Supply (1.7 V to 5.5 V).
24
VOUT4
LDO2 Output Voltage.
EPAD (EP) Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane.
ADP5037 Data Sheet
Rev. B | Page 8 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1= VIN2 = VIN3= VIN4 = 3.6 V, TA = 25°C, unless otherwise noted.
0
20
40
60
80
100
120
140
2.3 2.8 3.3 3.8 4.3 4.8 5.3
INP UT VOLTAGE (V)
QUIESCE NT CURRENT ( µ A)
09887-039
Figure 3. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V,
VOUT2 = 1.8 V, VOUT3 = 1.2 V, VOUT4 = 3.3 V, All Channels Unloaded
4
1
3
T
2
CH1 2.00V
BW
CH4 5.00V
BW
M40.0µs A CH3 2.2V
T11.20%
CH250.0mAΩ
BW
CH3 5.00V
BW
SW
IOUT
VOUT
EN
09887-049
Figure 4. BUCK1 Startup, VOUT1 = 1.8 V, IOUT1 = 5 mA
4
1
3
T
2
CH1 2.00V CH4 5.00V M 40.0µs A CH3 2.2V
T 11.20%
BW
CH2 50.0mA Ω
BW
BW
CH3 5.00V
BW
SW
IOUT
VOUT
EN
09887-048
Figure 5. BUCK2 Startup, VOUT2 = 3.3 V, IOUT2 = 10 mA
3.310
3.270
3.275
3.280
3.285
3.290
3.295
3.300
3.305
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VOUT (V)
IOUT (A)
–40°C
+25°C
+85°C
09887-100
Figure 6. BUCK1 Load Regulation Across Temperature, VIN = 4.2 V,
VOUT1 = 3.3 V, Auto Mode
1.812
1.798
1.800
1.802
1.804
1.806
1.808
1.810
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VOUT (V)
IOUT (A)
–40°C
+25°C
+85°C
09887-101
Figure 7. BUCK2 Load Regulation Across Temperature, VIN = 3.6 V,
VOUT2 = 1.8 V, Auto Mode
0.808
0.802
0.803
0.804
0.805
0.806
0.807
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VOUT (V)
IOUT (A)
–40°C +25°C
+85°C
09887-102
Figure 8. BUCK1 Load Regulation Across Input Voltage, VIN = 3.6 V,
VOUT1 = 0.8 V, PWM Mode
Data Sheet ADP5037
Rev. B | Page 9 of 28
100
90
80
70
60
50
40
30
20
10
0110 100 1000
EF FICIENCY ( %)
ILOAD (mA)
VIN = 2.3V
VIN = 3.6V VIN = 4.2V VIN = 5.5V
09887-103
Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0110 100 1000
EF FICIENCY ( %)
ILOAD (mA)
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
09887-104
Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, PWM Mode
100
90
80
70
60
50
40
30
20
10
0110 100 1000
EF FICIENCY ( %)
ILOAD (mA)
VIN = 2.3V
VIN = 3.6V VIN = 4.2V VIN = 5.5V
09887-105
Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VOUT2 = 1.8 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0110 100 1000
EF FICIENCY ( %)
ILOAD (mA)
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
09887-106
Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VOUT2 = 1.8 V, PWM Mode
100
90
80
70
60
50
40
30
20
10
0110 100 1000
EF FICIENCY ( %)
ILOAD (mA)
VIN = 2.3V VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
09887-107
Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 0.8 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0110 100 1000
EF FICIENCY ( %)
ILOAD (mA)
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
09887-108
Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 0.8 V, PWM Mode
ADP5037 Data Sheet
Rev. B | Page 10 of 28
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
EFFICIENCY (%)
I
OUT
(A)
–40°C
+25°C
+85°C
09887-028
Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature,
VIN = 3.9 V, VOUT1 = 3.3 V, Auto Mode
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
EFFICIENCY (%)
I
OUT
(A)
+85°C
+25°C
–40°C
09887-030
Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature,
VOUT2 = 1.8 V, Auto Mode
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
EFFICIENCY (%)
I
OUT
(A)
+85°C
+25°C
–40°C
09887-029
Figure 17. BUCK1 Efficiency vs. Load Current, Across Temperature
VOUT1 = 0.8 V, Auto Mode
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
00.2 0.4 0.6 0.8 1.0 1.2
FREQUENCY (MHz)
I
OUT
(A)
+85°C
+25°C
–40°C
09887-031
Figure 18. BUCK2 Switching Frequency vs. Output Current, Across
Temperature, VOUT2 = 1.8 V, PWM Mode
2
4
T
1
CH1 50.0mV M 4. 00µ s A CH2 240mA
T 28.40%
CH2 500mA Ω
CH4 2.00V
I
SW
VOUT
SW
09887-051
Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
2
4
T
1
CH1 50.0mV
BW
M 4. 00µ s A CH2 220mA
T 28.40%
CH2 500mA Ω
CH4 2.00V
BW
I
SW
VOUT
SW
09887-050
Figure 20. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Auto Mode
Data Sheet ADP5037
Rev. B | Page 11 of 28
2
4
T
1
CH1 50mV
BW
M 400n s A CH2 220mA
T 28.40%
CH2 500mA Ω
CH4 2.00V
BW
I
SW
VOUT
SW
09887-053
Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
2
4
T
1
CH1 50mV
BW
M 400n s A CH2 220mA
T 28.40%
CH2 500mA Ω
CH4 2.00V
BW
I
SW
VOUT
SW
09887-052
Figure 22. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode
CH1 50.0mV
BW
CH3 1.00V
BW
CH4 2.00V
BW
M 1. 00ms A CH3 4.80V
1
3
T 30.40%
T
VOUT
VIN
SW
09887-040
Figure 23. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, VOUT1 = 3.3 V, PWM Mode
1
4
T
3
CH1 50.0mV
BW
CH3 1.00V
BW
CH4 2.00V
BW
M 1. 00ms A CH3 4.80V
T 30.40%
VOUT
VIN
SW
09887-041
Figure 24. BUCK2 Response to Line Transient, VIN2 = 4.5 V to 5.0 V,
VOUT2 = 1.8 V, PWM Mode
4
1
T
2
CH1 50.0mV
BW
CH4 5.00V
BW
M 20. 0µ s A CH2 356mA
T 60.000µ s
CH2 50.0mA Ω
BW
VOUT
I
OUT
SW
09887-044
Figure 25. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA,
VOUT1 = 3.3 V, Auto Mode
4
1
T
2
CH1 50.0mV BWCH4 5.00V BWM 20. 0µ s A CH2 379mA
T 22.20%
CH2 50.0mA Ω BW
VOUT
IOUT
SW
09887-043
Figure 26. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA,
VOUT2 = 1.8 V, Auto Mode
ADP5037 Data Sheet
Rev. B | Page 12 of 28
4
2
T
1
CH1 50.0mV BWCH4 5.00V BWM 20. 0µ s A CH2 408mA
T 20.40%
CH2 200mA Ω BW
VOUT
IOUT
SW
09887-045
Figure 27. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA,
VOUT1 = 3.3 V, Auto Mode
4
2
T
1
CH1 100mV
BW
CH4 5.00V
BW
M 20. 0µ s A CH2 88.0mA
T 19.20%
CH2 200mA Ω
BW
VOUT
I
OUT
SW
09887-046
Figure 28. BUCK2 Response to Load Transient, IOUT2 from 20 mA to 180 mA,
VOUT2 = 1.8 V, Auto Mode
4
1
3
T
2
CH1 5.00V
BW
CH4 5.00V
BW
M 400n s A CH4 1.90V
T 50.00%
CH2 5.00V
BW
CH3 5.00V
BW
VOUT1
VOUT2
SW1
SW2
09887-060
Figure 29. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode
Showing Out-of-Phase Operation
CH1 100mA
CH3 1.00V CH2 5.0V M40.0µs 2.5GS/s A CH2 4.20V
2
3
1
T 159.4µ s
EN
VOUT
I
IN
09887-109
Figure 30. LDO Startup, VOUT3 = 1.8 V
3.304
3.303
3.302
3.301
3.300
3.299
3.298
3.297
3.296
3.295
3.29400.1 0.2 0.3
VOUT (V)
IOUT (A)
VIN = 3.8V
VIN = 4.2V
VIN = 5.5V
09887-110
Figure 31. LDO Load Regulation Across Input Voltage, VOUT3 = 3.3 V
0
50
100
150
200
250
300
350
400
2.3 2.8 3.3 3.8 4.3 4.8 5.3
RDSON (mΩ)
INP UT VOLTAGE (V)
+25°C +125°C
–40°C
09887-037
Figure 32. NMOS RDSON vs. Input Voltage Across Temperature
Data Sheet ADP5037
Rev. B | Page 13 of 28
2.3 2.8 3.3 3.8 4.3 4.8 5.3
RDS
ON
(mΩ)
INP UT VOLTAGE (V)
+125°C
+25°C
–40°C
0
50
100
150
200
250
09887-038
Figure 33. PMOS RDSON vs. Input Voltage Across Temperature
1.802
1.801
1.800
1.799
1.798
1.797
1.796
1.795
1.794
1.793
1.79200.1 0.2 0.3
VOUT (V)
IOUT (A)
–40°C
+25°C
+85°C
09887-111
Figure 34. LDO Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 1.8 V
0
0.5
1.0
1.5
2.0
2.5
3.0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
V
IN
(V)
I
OUT
= 300m A
I
OUT
= 150m A
I
OUT
= 100m A
I
OUT
= 1mA
I
OUT
= 10mA I
OUT
= 100µA
09887-034
V
OUT
(V)
Figure 35. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V
00.05 0.10 0.15 0.20 0.25
GROUND CURRENT ( µ A)
LOAD CURRENT ( A)
0
5
10
15
20
25
30
35
40
45
50
09887-036
Figure 36. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
2
T
1
CH1 100mV
BW
M 40. 0µ s A CH2 52.0mA
T 19.20%
CH2 100mA Ω
BW
VOUT
I
OUT
09887-047
Figure 37. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA,
VOUT3 = 2.8 V
2
3
T
1
CH1 20.0mV
CH3 1.00V M 100µs A CH3 4. 80V
T 28.40%
VOUT
VIN
09887-042
Figure 38. LDO Response to Line Transient, Input Voltage from 4.5 V to 5 V,
VOUT3 = 2.8 V
ADP5037 Data Sheet
Rev. B | Page 14 of 28
60
55
50
45
40
35
30
25
0.001 0.01 0.1 110 100
ILOAD (mA)
RMS NOISE (µV)
VIN = 3.3V
VIN = 5V
09887-055
Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage,
VOUT3 = 2.8 V
60
65
55
50
45
40
35
30
25
0.001 0.01 0.1 110 100
I
LOAD
(mA)
RMS NOISE (µV)
09887-056
V
IN
= 3.3V
V
IN
= 5V
Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage,
VOUT3 = 3.0 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
100µA
1mA
10mA
50mA
100mA
150mA
09887-057
Figure 41. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
0
–20
–40
–60
–80
–100
–12010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
100µA
1mA
10mA
50mA
100mA
150mA
09887-058
Figure 42. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V
0
–20
–40
–60
–80
–100
–12010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
100µA
1mA
10mA
50mA
100mA
150mA
09887-059
Figure 43. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
100µA
1mA
10mA
50mA
100mA
150mA
09887-061
Figure 44. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V
Data Sheet ADP5037
Rev. B | Page 15 of 28
THEORY OF OPERATION
LDO
CONTROL
LDO
UNDERVOLTAGE
LOCKOUT
SOFT START
PWM/
PSM
CONTROL
BUCK2
DRIVER
AND
ANTISHOOT
THROUGH
SOFT START
DRIVER
AND
ANTISHOOT
THROUGH
OSCILLATOR
THERMAL
SHUTDOWN
SYSTEM
UNDERVOLTAGE
LOCKOUT
PWM
COMP
GM E RROR
AMP GM E RROR
AMP
PSM
COMP PSM
COMP
LOW
CURRENT
I
LIMIT
PWM
COMP
LOW
CURRENT
I
LIMIT
R1
R2
ADP5037
VOUT1 VOUT2
VIN1
AVIN
SW1
PGND1
VIN3 AGND VOUT3
FB3
PGND2
SW2
VIN2
AVIN
75Ω
ENBK1
ENABLE
AND
MODE
CONTROL
EN1 ENBK1
ENBK2
ENLDO1
ENLDO2
600Ω
ENLDO2
75Ω
ENBK2
EN2
EN3
EN4
600Ω
ENLDO1
LDO
CONTROL
LDO
UNDERVOLTAGE
LOCKOUT
R3
R4
VIN4 VOUT4
AVIN
FB4
B
SEL
OP
MODE
MODE2
A
Y
MODE
FB1 FB2
PWM/
PSM
CONTROL
BUCK1
09887-005
Figure 45. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5037 is a micropower management units (micro PMU)
combining two step-down (buck) dc-to-dc convertors and
two low dropout linear regulators (LDOs). The high switching
frequency and tiny 24-lead LFCSP package allow for a small
power management solution.
To combine these high performance regulators into the micro
PMU, there is a system controller allowing them to operate
together.
The buck regulators can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
buck switching frequency is always constant and does not
change with the load current. If the MODE pin is at logic low
level, the switching regulators operate in auto PWM/PSM
mode. In this mode, the regulators operate at fixed PWM
frequency when the load current is above the PSM current
threshold. When the load current falls below the PSM current
threshold, the regulator in question enters PSM, where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent current
losses. The auto PWM/PSM mode transition is controlled
independently for each buck regulator. The two bucks operate
synchronized to each other.
The ADP5037 has individual enable pins (EN1 to EN4) control-
ling the activation of each regulator. The regulators are activated
by a logic level high applied to the respective EN pin. EN1 controls
BUCK1, EN2 controls BUCK2, EN3 controls LDO1, and EN4
controls LDO2.
Regulator output voltages are set through external resistor
dividers or can be optionally factory programmed to default
values (see the Ordering Guide section).
When a regulator is turned on, the output voltage ramp rate is
controlled though a soft start circuit to avoid a large inrush
current due to the charging of the output capacitors.
ADP5037 Data Sheet
Rev. B | Page 16 of 28
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators. Extreme
junction temperatures can be the result of high current operation,
poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the regulators do not return to operation until the on-chip
temperature drops below 130°C. When coming out of thermal
shutdown, all regulators restart with soft start control.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated into the system. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channels, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V supply applications. For
these models, the device reaches the turn-off threshold when
the input supply drops to 3.65 V typical.
In case of a thermal or UVLO event, the active pull-downs (if
factory enabled) are enabled to discharge the output capacitors
quickly. The pull-down resistors remain engaged until the thermal
fault event is no longer present, or the input supply voltage falls
below the VPOR voltage level. The typical value of VPOR is approx-
imately 1 V.
Enable/Shutdown
The ADP5037 has an individual control pin for each regulator.
A logic level high applied to the ENx pin activates a regulator,
whereas a logic level low turns off a regulator.
Figure 46 shows the regulator activation timings for the ADP5037
when all enable pins are connected to AVIN. Also shown is the
active pull-down activation.
AVIN
VOUT3
VOUT4
VOUT1
VUVLO
VOUT2
VPOR
BUCK2
PULL-DOWN
BUCK1,
LDO1,
LDO2
PULL-DOWNS
50µs ( M IN)
30µs
(MIN) 50µs ( M IN)
30µs
(MIN)
09887-006
Figure 46. Regulator Sequencing on the ADP5037 (EN1 = EN2 = EN3 = EN4 = VAVIN)
Data Sheet ADP5037
Rev. B | Page 17 of 28
BUCK1 AND BUCK2
The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.
The buck output voltage is set through external resistor dividers,
shown in Figure 47 for BUCK1. The output voltage can optionally
be factory programmed to default values as indicated in the
Ordering Guide section. In this event, R1 and R2 are not needed,
and FB1 can be left unconnected. In all cases, VOUT1 must be
connected to the output capacitor. FB1 is 0.5 V.
BUCK
PGND1
FB1
SW1
R1
R2
VOUT1
VOUT1
VIN1 L1
1µH
C5
10µF
VOUT1 = VFB1 + 1
R1
R2
09887-008
Figure 47. BUCK1 External Output Voltage Setting
Control Scheme
The bucks operate with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency
but shift to a power save mode (PSM) control scheme at light
loads to lower the regulation power losses. When operating in
fixed frequency PWM mode, the duty cycle of the integrated
switches is adjusted and regulates the output voltage. When
operating in PSM at light loads, the output voltage is controlled
in a hysteretic manner, with higher output voltage ripple. During
part of this time, the converter is able to stop switching and
enters an idle mode, which improves conversion efficiency.
PWM Mode
In PWM mode, the bucks operate at a fixed frequency of 3 MHz
set by an internal oscillator. At the start of each oscillator cycle,
the pFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the pFET switch and turns on the nFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
Power Save Mode (PSM)
The bucks smoothly transition to PSM operation when the load
current decreases below the PSM current threshold. When either of
the bucks enters PSM, an offset is induced in the PWM regulation
level, which makes the output voltage rise. When the output voltage
reaches a level approximately 1.5% above the PWM regulation
level, PWM operation is turned off. At this point, both power
switches are off, and the buck enters an idle mode. The output
capacitor discharges until the output voltage falls to the PWM
regulation voltage, at which point the device drives the inductor
to make the output voltage rise again to the upper threshold.
This process is repeated while the load current is below the PSM
current threshold.
The ADP5037 has a dedicated MODE pin controlling the PSM
and PWM operation. A high logic level applied to the MODE
pin forces both bucks to operate in PWM mode. A logic level
low sets the bucks to operate in auto PSM/PWM.
PSM Current Threshold
The PSM current threshold is set to100 mA. The bucks employ
a scheme that enables this current to remain accurately controlled,
independent of input and output voltage levels. This scheme
also ensures that there is very little hysteresis between the PSM
current threshold for entry to and exit from the PSM. The PSM
current threshold is optimized for excellent efficiency over all
load currents.
Oscillator/Phasing of Inductor Switching
The ADP5037 ensures that both bucks operate at the same
switching frequency when both bucks are in PWM mode.
Additionally, the ADP5037 ensures that when both bucks are in
PWM mode, they operate out of phase, whereby the BUCK2 pFET
starts conducting exactly half a clock period after the BUCK1
pFET starts conducting.
Short-Circuit Protection
The bucks include frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin falls
below half the target output voltage, indicating the possibility of
a hard short at the output, the switching frequency is reduced to
half the internal oscillator frequency. The reduction in the
switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
Soft Start
The bucks have an internal soft start function that ramps the output
voltage in a controlled manner upon startup, thereby limiting
the inrush current. This prevents possible input voltage drops
when a battery or a high impedance power source is connected
to the input of the converter.
Current Limit
Each buck has protection circuitry to limit the amount of
positive current flowing through the pFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
ADP5037 Data Sheet
Rev. B | Page 18 of 28
100% Duty Operation
With a drop in input voltage, or with an increase in load current,
the buck may reach a limit where, even with the pFET switch
on 100% of the time, the output voltage drops below the desired
output voltage. At this limit, the buck transitions to a mode where
the pFET switch stays on 100% of the time. When the input
conditions change again and the required duty cycle falls, the
buck immediately restarts PWM regulation without allowing
overshoot on the output voltage.
Active Pull-Downs
All regulators have optional, factory programmable, active pull-
down resistors discharging the respective output capacitors
when the regulators are disabled. The pull-down resistors are
connected between VOUTx and AGND. Active pull-downs are
disabled when the regulators are turned on. The typical value of
the pull-down resistor is 600 Ω for the LDOs and 75 Ω for the
bucks. Figure 46 shows the activation timings for the active
pull-downs during regulator activation and deactivation.
LDO1 AND LDO2
The ADP5037 contains two LDOs with low quiescent current
and low dropout voltage, and provides up to 300 mA of output
current. Drawing a low 10 μA quiescent current (typical) at no load
makes the LDO ideal for battery-operated portable equipment.
Each LDO operates with an input voltage of 1.7 V to 5.5 V. The
wide operating range makes these LDOs suitable for cascading
configurations where the LDO supply voltage is provided from
one of the buck regulators.
Each LDO output voltage is set through external resistor dividers
as shown in Figure 48 for LDO1. The output voltage can optionally
be factory programmed to default values as indicated in the
Ordering Guide section. In this event, Ra and Rb are not needed,
and FB3 must be connected to the top of the capacitor on
VOUT3. FB3 is 0.5 V.
LDO1 FB3 Ra
Rb
VOUT3 VOUT3
VIN3 C7
1µF
V
OUT3
= V
FB3
+ 1
Ra
Rb
09887-009
Figure 48. LDO1 External Output Voltage Setting
The LDOs also provide high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with only a small 1 µF ceramic input and output capacitor.
LDO1 is optimized to supply analog circuits because it offers
better noise performance compared to LDO2. LDO1 should be
used in applications where noise performance is critical.
Data Sheet ADP5037
Rev. B | Page 19 of 28
APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.
Feedback Resistors
For the adjustable model, referring to Figure 47, the total
combined resistance for R1 and R2 is not to exceed 400 kΩ.
Inductor
The high switching frequency of the ADP5037 bucks allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 μH and 3 μH. Suggested inductors
are shown in Table 8.
The peak-to-peak inductor current ripple is calculated using
the following equation:
LfV
VVV
I
SW
IN
OUT
IN
OUT
RIPPLE ××
−×
=)(
where:
fSW is the switching frequency.
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
2
)(
RIPPLE
MAXLOAD
PEAK
I
II +=
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the bucks are high switching frequency dc-to-dc
converters, shielded ferrite core material is recommended for
its low core losses and low EMI.
Output Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
dc-to-dc converter because of their poor temperature and dc
bias characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated
using the following equation:
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT is 9.2 μF at 1.8 V, as shown in Figure 49.
Substituting these values in the equation yields
CEFF = 9.2 μF × (1 − 0.15) × (1 − 0.1) = 7.0 μF
To guarantee the performance of the bucks, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
0
2
4
6
8
10
12
0123456
DC BIAS V OLTAGE ( V )
CAPACI TANCE (µ F)
09887-010
Figure 49. Capacitance vs. Voltage Characteristic
Table 8. Suggested 1.0 μH Inductors
Vendor Model Dimensions (mm) ISAT (mA) DCR (mΩ)
Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85
Murata LQM18FN1R0M00B 3.2 × 2.5 × 1.5 2300 54
Taiyo Yuden
CBC3225T1R0MR
3.2 × 2.5 × 2.5
2000
71
Coilcraft XFL4020-102ME 4.0 × 4.0 × 2.1 5400 11
Coilcraft XPL2010-102ML 1.9 × 2.0 × 1.0 3750 89
Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85
ADP5037 Data Sheet
Rev. B | Page 20 of 28
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
OUTSW
IN
OUTSW
RIPPLE
RIPPLE CLf
V
Cf
I
V×××
≈
××
=2
)2(
8
π
Capacitors with lower effective series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
RIPPLE
RIPPLE
COUT
I
V
ESR ≤
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.
The buck regulators require 10 µF output capacitors to guarantee
stability and response to rapid load variations and to transition into
and out of the PWM/PSM modes. A list of suggested capacitors is
shown in Table 9. In certain applications where one or both buck
regulator powers a processor, the operating state is known
because it is controlled by software. In this condition, the
processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 µF to 4.7 µF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 50).
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
IN
OUT
IN
OUT
MAXLOAD
CIN
V
VVV
II )(
)(
−
≥
To minimize supply noise, place the input capacitor as close as
possible to the VINx pin of the buck. As with the output capacitor,
a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Table 9 and Table 10.
Table 9. Suggested 10 μF Capacitors
Vendor Type Model
Case
Size
Voltage
Rating
(V)
Murata X5R GRM188R60J106 0603 6.3
TDK X5R C1608JB0J106K 0603 6.3
Panasonic X5R ECJ1VB0J106M 0603 6.3
Table 10. Suggested 4.7 μF Capacitors
Vendor Type Model
Case
Size
Voltage
Rating
(V)
Murata X5R GRM188R60J475ME19D 0402 6.3
Taiyo Yuden X5R JMK107BJ475 0402 6.3
Panasonic X5R ECJ-0EB0J475M 0402 6.3
Table 11. Suggested 1.0 μF Capacitors
Vendor Type Model
Case
Size
Voltage
Rating (V)
Murata X5R GRM155B30J105K 0402 6.3
TDK X5R C1005JB0J105KT 0402 6.3
Panasonic X5R ECJ0EB0J105K 0402 6.3
Taiyo
Yuden
X5R LMK105BJ105MV-F 0402 10.0
VIN1
VIN3
EN1 PWM
PSM/PWM
2.3V TO
5.5V SW1
FB1
R2
R1
VOUT1
PGND1
MODE
C5
10µF
V
OUT1
@
800mA
L1 1µH
EN1
BUCK1
MODE
C3
1µF
C2
4.7µF
C1
4.7µF
AVIN
C
AVIN
0.1µF
C4
1µF
VIN2
EN2
AGND
EN2
BUCK2
MODE
EN3
1.7V TO
5.5V
EN4
VIN4
ON
OFF
ON
OFF
ON
OFF
EN3 LDO1
(ANALOG)
ADP5037
HOUSEKEEPING
SW2
FB2
R4
R3
VOUT2
PGND2 C6
10µF
V
OUT2
@
800mA
L2 1µH
FB3
R6
R5
VOUT3
C7
1µF
V
OUT3
@
300mA
FB4
R8
R7
VOUT4
C8
1µF
V
OUT4
@
300mA
EN4 LDO2
(DIGITAL)
09887-021
Figure 50. Processor System Power Management with PSM/PWM Control
Data Sheet ADP5037
Rev. B | Page 21 of 28
LDO EXTERNAL COMPONENT SELECTION
Feedback Resistors
For the adjustable model, the maximum value of Rb is not to
exceed 200 kΩ (see Figure 48).
Output Capacitor
The ADP5037 LDOs are designed for operation with small, space-
saving ceramic capacitors, but function with most commonly
used capacitors as long as care is taken with the ESR value. The
ESR of the output capacitor affects stability of the LDO control
loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or
less is recommended to ensure that stability of the ADP5037.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP5037 to large
changes in load current.
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN3 and VIN4 to ground
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source impedance
is encountered. If greater than 1 µF of output capacitance is
required, increase the input capacitor to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5037 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
LDO because of their poor temperature and dc bias characteristics.
Figure 51 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or with higher
voltage rating exhibits better stability. The temperature variation
of the X5R dielectric is about ±15% over the −40°C to +85°C
temperature range and is not a function of package or voltage
rating.
1.2
1.0
0.8
0.6
0.4
0.2
00 1 2 3 4 5 6
DC BIAS V OLTAGE ( V )
CAPACI TANCE (µ F)
09887-012
Figure 51. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capa-
citance accounting for capacitor variation over temperature,
component tolerance, and voltage:
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 0.85 μF at 1.8 V as shown in Figure 51.
Substituting these values into the following equation,
CEFF = 0.85 μF × (1 − 0.15) × (1 − 0.1) ≈ 0.65 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5037, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
ADP5037 Data Sheet
Rev. B | Page 22 of 28
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The ADP5037 is a highly efficient µPMU, and, in most cases, the
power dissipated in the device is not a concern. However, if the
device operates at high ambient temperatures and maximum
loading condition, the junction temperature can reach the
maximum allowable operating limit (125°C).
When the temperature exceeds 150°C, the ADP5037 turns off
all the regulators, allowing the device to cool down. When the
die temperature falls below 130°C, the ADP5037 resumes
normal operation.
This section provides guidelines to calculate the power dissipated
in the device and ensure that the ADP5037 operates below the
maximum allowable junction temperature.
The efficiency for each regulator on the ADP5037 is given by
100%×=
IN
OUT
P
P
η
(1)
where:
η is the efficiency.
PIN is the input power.
POUT is the output power.
Power loss is given by
PLOSS = PIN − POUT (2a)
or
PLOSS = POUT (1− η)/η (2b)
Power dissipation can be calculated in several ways. The most
intuitive and practical is to measure the power dissipated at the
input and all the outputs. Perform the measurements at the
worst-case conditions (voltages, currents, and temperature).
The difference between input and output power is dissipated in
the device and the inductor. Use Equation 4 to derive the power
lost in the inductor and, from this, use Equation 3 to calculate
the power dissipation in the ADP5037 buck converter.
A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator, and the power
lost on each LDO can be calculated using Equation 12. When
the buck efficiency is known, use Equation 2b to derive the total
power lost in the buck regulator and inductor, use Equation 4 to
derive the power lost in the inductor, and then calculate the
power dissipation in the buck converter using Equation 3. Add
the power dissipated in the buck and in the two LDOs to find
the total dissipated power.
Note that the buck efficiency curves are typical values and may
not be provided for all possible combinations of VIN, VOUT, and
IOU T. To account for these variations, it is necessary to include a
safety margin when calculating the power dissipated in the buck.
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11 and the losses in the LDO provided
by Equation 12.
BUCK REGULATOR POWER DISSIPATION
The power loss of the buck regulator is approximated by
PLOSS = PDBUCK + PL (3)
where:
PDBUCK is the power dissipation on one of the ADP5037 buck
regulators.
PL is the inductor power losses.
The inductor losses are external to the device, and they do not
have any effect on the die temperature.
The inductor losses are estimated (without core losses) by
PL ≈ IOUT1(RMS)
2 × DCRL (4)
where:
DCRL is the inductor series resistance.
IOUT1(RMS) is the rms load current of the buck regulator.
12
+1
)(
1
r
I
I
OUT1
RMSOUT
×
=
(5)
where r is the normalized inductor ripple current.
r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6)
where:
L is the inductance.
fSW is the switching frequency.
D is the duty cycle.
D = VOUT1/VIN1 (7)
The ADP5037 buck regulator power dissipation, PDBUCK, includes
the power switch conductive losses, the switch losses, and the
transition losses of each channel. There are other sources of
loss, but these are generally less significant at high output load
currents, where the thermal limit of the application is. Equation
8 captures the calculation that must be made to estimate the
power dissipation in the buck regulator.
PDBUCK = PCOND + PSW + PTRAN (8)
The power switch conductive losses are due to the output current,
IOUT1, flowing through the P-MOSFET and the N-MOSFET
power switches that have internal resistance, RDSON-P and
RDSON-N. The amount of conductive power loss is found by
PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT1(RMS)
2 (9)
where RDSON-P is approximately 0.2 Ω, and RDSON-N is approxi-
mately 0.16 Ω at 25°C junction temperature and VIN1 = VIN2 =
3.6 V. At VIN1 = VIN2 = 2.3 V, these values change to 0.31 Ω and
0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V, the values are
0.16 Ω and 0.14 Ω, respectively.
Data Sheet ADP5037
Rev. B | Page 23 of 28
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
PSW = (CGATE-P + CGATE-N) × VIN1
2 × fSW (10)
where:
CGATE-P is the P-MOSFET gate capacitance.
CGATE-N is the N-MOSFET gate capacitance.
For the ADP5037, the total of (CGATE-P + CGATE-N) is
approximately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
VOUT1 (and from VOUT1 to ground). The amount of transition
loss is calculated by
PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11)
where tRISE and tFALL are the rise time and the fall time of the
switching node, SW. For the ADP5037, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimat-
ing the converter efficiency, it must be noted that the equations
do not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by
PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (12)
where:
ILOAD is the load current of the LDO regulator.
VIN and VOUT are input and output voltages of the LDO,
respectively.
IGND is the ground current of the LDO regulator.
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the ADP5037 simplifies to
PD = PDBUCK1 + PDBUCK2 + PDLDO1 + PDLDO2 (13)
JUNCTION TEMPERATURE
In cases where the board temperature, TA, is known, the thermal
resistance parameter, θJA, can be used to estimate the junction
temperature rise. TJ is calculated from TA and PD using the
formula
TJ = TA + (PD × θJA) (14)
The typical θJA value for the 24-lead, 4 mm × 4 mm LFCSP is
35°C/W (see Table 6). A very important factor to consider is
that θJA is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per
JEDEC standard, and real applications may use different sizes
and layers. It is important to maximize the copper used to remove
the heat from the device. Copper exposed to air dissipates heat
better than copper used in the inner layers. The exposed pad
should be connected to the ground plane with several vias.
If the case temperature can be measured, the junction
temperature is calculated by
TJ = TC + (PD × θJC) (15)
where TC is the case temperature and θJC is the junction-to-case
thermal resistance provided in Table 6.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5037 power
dissipation (PD) due to the losses of all channels by using the
Equation 8 to Equation 13. From this power calculation, the
junction temperature, TJ, can be estimated using Equation 14.
The reliable operation of the converter and the two LDO regulators
can be achieved only if the estimated die junction temperature of
the ADP5037 (Equation 14) is less than 125°C. Reliability and
mean time between failures (MTBF) are highly affected by increas-
ing the junction temperature. Additional information about
product reliability can be found from the ADI Reliability Handbook,
which can be found at www.analog.com/reliability_handbook.
ADP5037 Data Sheet
Rev. B | Page 24 of 28
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5037 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor layout
can also affect regulation and stability. A good layout is
implemented using the following guidelines.
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
• Connect VIN1, VIN2, and AVIN together close to the IC
using short tracks.
In addition, refer to the UG-271 User Guide.
Data Sheet ADP5037
Rev. B | Page 25 of 28
TYPICAL APPLICATION SCHEMATICS
VIN1
VIN3
EN1 PWM
PSM/PWM
2.3V TO
5.5V SW1
FB1
VOUT1
PGND1
MODE
C5
10µF
V
OUT1
@
800mA
L1 1µH
EN1
BUCK1
MODE
C3
1µF
C2
4.7µF
C1
4.7µF
AVIN
C
AVIN
0.1µF
C4
1µF
VIN2
EN2
AGND
EN2
BUCK2
MODE
EN3
1.7V TO
5.5V
EN4
VIN4
ON
OFF
ON
OFF
ON
OFF
EN3 LDO1
(ANALOG)
ADP5037
HOUSEKEEPING
SW2
FB2 R3
VOUT2
PGND2 C6
10µF
V
OUT2
@
800mA
L2 1µH
FB3
VOUT3
C7
1µF
V
OUT3
@
300mA
FB4
VOUT4
C8
1µF
V
OUT4
@
300mA
EN4 LDO2
(DIGITAL)
09887-022
Figure 52. ADP5037 Fixed Output Voltages with Enable Pins
VIN1
VIN3
EN1 PWM
PSM/PWM
2.3V TO
5.5V SW1
FB1
R2
R1
VOUT1
PGND1
MODE
C5
10µF
V
OUT1
@
800mA
L1 1µH
EN1
BUCK1
MODE
C3
1µF
C2
4.7µF
C1
4.7µF
AVIN
C
AVIN
0.1µF
C4
1µF
VIN2
EN2
AGND
EN2
BUCK2
MODE
EN3
1.7V TO
5.5V
EN4
VIN4
ON
OFF
ON
OFF
ON
OFF
EN3 LDO1
(ANALOG)
ADP5037
HOUSEKEEPING
SW2
FB2
R4
R3
VOUT2
PGND2 C6
10µF
V
OUT2
@
800mA
L2 1µH
FB3
R6
R5
VOUT3
C7
1µF
V
OUT3
@
300mA
FB4
R8
R7
VOUT4
C8
1µF
V
OUT4
@
300mA
EN4 LDO2
(DIGITAL)
09887-023
Figure 53. ADP5037 Adjustable Output Voltages with Enable Pins
ADP5037 Data Sheet
Rev. B | Page 26 of 28
BILL OF MATERIALS
Table 12.
Reference Value Part Number Vendor Package or Dimension (mm)
C
AVIN
0.1 µF, X5R, 6.3 V JMK105BJ104MV-F Taiyo-Yuden 0402
C3, C4, C7, C8 1 µF, X5R, 6.3 V LMK105BJ105MV-F Taiyo-Yuden 0402
C1, C2 4.7 µF, X5R, 6.3 V ECJ-0EB0J475M Panasonic-ECG 0402
C5, C6 10 µF, X5R, 6.3 V JMK107BJ106MA-T Taiyo-Yuden 0603
L1, L2 1 µH, 0.18 Ω, 850 mA BRC1608T1R0M Taiyo-Yuden 0603
1 µH, 0.085 Ω, 1400 mA LQM2MPN1R0NG0B Murata 2.0 × 1.6 × 0.9
1 µH, 0.059 Ω, 900 mA
EPL2014-102ML
Coilcraft
2.0 × 2.0 × 1.4
1 µH, 0.086 Ω, 1350 mA MDT2520-CN Toko 2.5 × 2.0 × 1.2
IC1 Four-regulator micro PMU ADP5037 Analog Devices 24-lead LFCSP
Data Sheet ADP5037
Rev. B | Page 27 of 28
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC S TANDARDS MO-220-WGGD-8.
06-11-2012-A
BOTTOM VIEWTOP VI EW
EXPOSED
PAD
PI N 1
INDICATOR
4.10
4.00 S Q
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 RE F
0.25 M IN
COPLANARITY
0.08
PI N 1
INDICATOR
2.20
2.10 S Q
2.00
1
24
7
12
13
1819
6
FOR PRO P E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATION AND
FUNCTION DESCRIPT IONS
SECTION OF THIS DATA SHEET.
0.05 M AX
0.02 NOM
Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
Range Output Voltage2 UVLO3 Active Pull-Down4 Package Description
Package
Option
ADP5037ACPZ-R7 −40°C to +125°C Adjustable Low Enabled on Buck Channels 24-Lead LFCSP_WQ CP-24-10
ADP5037ACPZ-1-R7 −40°C to +125°C VOUT1 = 1.2 V,
VOUT2 = 3.3 V,
VOUT3 = 2.8 V,
VOUT4 = 1.8 V
Low Enabled on Buck Channels 24-Lead LFCSP_WQ CP-24-10
ADP5037ACPZ-2-R7 −40°C to +125°C VOUT1 = 1.0 V,
VOUT2 = 1.8 V,
VOUT3 = 3.3 V,
VOUT4 = 2.8 V
Low Enabled on Buck and
LDO Channels
24-Lead LFCSP_WQ CP-24-10
ADP5037CP-EVALZ Evaluation Board for
ADP5037ACPZ-R7
1 Z = RoHS Compliant Part.
2 For additional options, contact a local sales or distribution representative. Additional options available are:
BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, or adjustable.
LDO1 and LDO2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V, or adjustable.
3 UVLO: low or high.
4 BUCK1, BUCK2, and both LDO1 and LDO2: active pull-down resistor is programmable to be either enabled or disabled.
