BQ4852YMC-85 - Texas Instruments

Features

➤Integrated SRAM, real-time

clock, CPU supervisor, crystal,

power-fail control circuit, and

battery

➤Real-Time Clock counts hun-

dredths of seconds through years

in BCD format

➤RAM-like clock access

➤Compatible with industry-

standard 512K x 8 SRAMs

➤Unlimited write cycles

➤10-year minimum data retention

and clock operation in the ab-

sence of power

➤Automatic power-fail chip dese-

lect and write-protection

➤Watchdog timer, power-on reset,

alarm/periodic interrupt, power-

fail and battery-low warning

➤Software clock calibration for

greater than ±1 minute per

month accuracy

General Description

The bq4852Y RTC Module is a non-

volatile 4,194,304-bit SRAM organ-

ized as 524,288 words by 8 bits with

an integral accessible real-time

clock and CPU supervisor. The CPU

supervisor provides a programmable

watchdog timer and a microproces-

sor reset. Other features include

alarm, power-fail, and periodic inter-

rupts,and a battery-low warning.

The device combines an internal lith-

ium battery, quartz crystal, clock and

power-fail chip, and a full CMOS

SRAM in a plastic 36-pin DIP mod-

ule. The RTC Module directly re-

places industry-standard SRAMs and

also fits into many EPROM and EE-

PROM sockets without any require-

ment for special write timing or limi-

tations on the number of write cycles.

Registers for the real-time clock,

alarm and other special functions

are located in registers 7FFF0h–

7FFFFh of the memory array.

The clock and alarm registers are

dual-port read/write SRAM loca-

tions that are updated once per sec-

ond by a clock control circuit from

the internal clock counters. The

dual-port registers allow clock up-

dates to occur without interrupting

normal access to the rest of the

SRAM array.

The bq4852Y also contains a power-

fail-detect circuit. The circuit dese-

lects the device whenever VCC falls

below tolerance, providing a high de-

gree of data security. The battery is

electrically isolated when shipped

from the factory to provide maxi-

mum battery capacity. The battery

remains disconnected until the first

application of VCC.

bq4852Y

Aug. 1996

RTC Module With 512Kx8 NVSRAM

PN485201.eps

36-Pin DIP Module

RST

A18

A16

A14

A12

DQ1

DQ2

VSS

DQ0

VCC

INT

A15

A17

A13

A11

A10

DQ7

DQ5

DQ4

DQ3

DQ6

Pin Names

A0–A18 Address input

CE Chip enable

RST Microprocessor reset

WE Write enable

OE Output enable

DQ0–DQ7Data in/data out

INT Programmable interrupt

VCC +5 volts

VSS Ground

Pin Connections

Not Recommended For New Designs

Functional Description

Figure 1 is a block diagram of the bq4852Y. The follow-

ing sections describe the bq4852Y functional operation,

including memory and clock interface, data-retention

modes, power-on reset timing, watchdog timer activa-

tion,and interrupt generation.

BD-962

16 1 MUX

INT

64648

AD -AD

018

Bus

I/F

Time-

Base

Oscillator

Control/Status

Registers

Clock/Calendar,

and Control Bytes

User Buffer

(16 Bytes)

Reset and

Generator

Clock/Calendar

Update

Power-

Fail

Control

DQ -DQ Interrupt RST

Storage

Registers

(524,288 Bytes)

Quartz

Internal

Crystal

Internal

Battery

Write-

Protect

Alarm,

Figure 1. Block Diagram

VCC CE OE WE Mode DQ Power

CC (max.) VIH X X Deselect High Z Standby

VIL XV

IL Write DIN Active

CC (min.) VIL VIL VIH Read DOUT Active

VIL VIH VIH Read High Z Active

PFD (min.) > VSO X X X Deselect High Z CMOS standby

≤VSO X X X Deselect High Z Battery-backup mode

Truth Table

Aug. 1996

bq4852Y

Not Recommended For New Designs

Address Map

The bq4852Y provides 16 bytes of clock and control status

registers and 524,272 bytes of storage RAM.

Figure 2 illustrates the address map for the bq4852Y. Table

1 is a map of the bq4852Y registers, and Table 2 describes

the register bits.

Memory Interface

Read Mode

The bq4852Y is in read mode whenever OE (output enable)

is low and CE (chip enable) is low. The device architecture

allows ripple-through access of data from eight of 4,194,304

locations in the static storage array. Thus, the unique ad-

dress specified by the 19 address inputs defines which one

of the 524,288 bytes of data is to be accessed. Valid data is

available at the data I/O pins within tAA (address access

time) after the last address input signal is stable, providing

that the CE and OE (output enable) access times are also

satisfied. If the CE and OE access times are not met, valid

data is available after the latter of chip enable access time

(tACE) or output enable access time (tOE).

CE and OE control the state of the eight three-state data

I/O signals. If the outputs are activated before tAA, the data

lines are driven to an indeterminate state until tAA. If the

address inputs are changed while CE and OE remain low,

output data remains valid for tOH (output data hold time),

but goes indeterminate until the next address access.

Write Mode

The bq4852Y is in write mode whenever WE and CE are

active. The start of a write is referenced from the latter-

occurring falling edge of WE or CE. A write is terminated

by the earlier rising edge of WE or CE. The addresses

must be held valid throughout the cycle. CE or WE must

return high for a minimum of tWR2 from CE or tWR1 from

WE prior to the initiation of another read or write cycle.

Data-in must be valid tDW prior to the end of write and re-

main valid for tDH1 or tDH2 afterward. OE should be kept

high during write cycles to avoid bus contention; although,

if the output bus has been activated by a low on CE and

OE,a low on WE disables the outputs tWZ after WE falls.

Data-Retention Mode

With valid VCC applied, the bq4852Y operates as a

conventional static RAM. Should the supply voltage

decay, the RAM automatically power-fail deselects,

write-protecting itself tWPT after VCC falls below VPFD.

All outputs become high impedance, and all inputs are

treated as “don’t care.”

If power-fail detection occurs during a valid access, the

memory cycle continues to completion. If the memory cycle

fails to terminate within time tWPT, write-protection takes

Registers

Control Status

Clock and

16 Bytes

RAM

Storage

Bytes

524,272

7FFFF

7FFEF

7FFF0

0000

7FFF2

7FFF3

7FFF4

7FFF5

7FFF6

7FFF7

7FFF8

7FFF9

7FFFA

7FFFC

7FFFD

7FFFE

Watchdog

Interrupts

Alarm Date

Alarm Hours

Alarm Minutes

Alarm Seconds

7FFFF

Control

Year

Month

Date

Days

Hours

Minutes

Seconds

FG4852Y1

Flags

Tenths/

Hundredths 7FFF1

7FFF0

7FFFB

Figure 2. Address Map

bq4852Y

Aug. 1996

Not Recommended For New Designs

place. When VCC drops below VSO, the control circuit

switches power to the internal energy source, which pre-

serves data.

The internal coin cell maintains data in the bq4852Y af-

ter the initial application of VCC for an accumulated period

of at least 10 years when VCC is less than VSO. As system

power returns and VCC rises above VSO, the battery is discon-

nected, and the power supply is switched to external VCC.

Write-protection continues for tCER after VCC reaches VPFD to

allow for processor stabilization. After tCER, normal RAM op-

eration can resume.

Clock Interface

Reading the Clock

The interface to the clock and control registers of the

bq4852Y is the same as that for the general-purpose

storage memory. Once every second, the user-accessible

clock/calendar locations are updated simultaneously

from the internal real time counters. To prevent reading

data in transition, updates to the bq4852Y clock regis-

ters should be halted. Updating is halted by setting the

read bit D6 of the control register to 1. As long as the

read bit is 1, updates to user-accessible clock locations

are inhibited. Once the frozen clock information is re-

trieved by reading the appropriate clock memory loca-

tions, the read bit should be reset to 0 in order to allow

updates to occur from the internal counters. Because

the internal counters are not halted by setting the read

bit, reading the clock locations has no effect on clock ac-

curacy. Once the read bit is reset to 0, within one second

the internal registers update the user-accessible regis-

ters with the correct time. A halt command issued dur-

ing a clock update allows the update to occur before

freezing the data.

Setting the Clock

Bit D7 of the control register is the write bit. Like the

read bit, the write bit when set to a 1 halts updates to

the clock/calendar memory locations. Once frozen, the

locations can be written with the desired information in

24-hour BCD format. Resetting the write bit to 0 causes

the written values to be transferred to the internal clock

counters and allows updates to the user-accessible regis-

ters to resume within one second. Use the write bit, D7,

only when updating the time registers (7FFFF–7FFF9).

Aug. 1996

Address D7 D6 D5 D4 D3 D2 D1 D0 Range (h) Register

7FFFF 10 Years Year 00–99 Year

7FFFF X X X 10 Month Month 01–12 Month

7FFFD X X 10 Date Date 01–31 Date

7FFFC X FTE X X X Day 01–07 Days

7FFFB X X 10 Hours Hours 00–23 Hours

7FFFA X 10 Minutes Minutes 00–59 Minutes

7FFF9 OSC 10 Seconds Seconds 00–59 Seconds

7FFF8 W R S Calibration 00–31 Control

7FFF7 WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0 Watchdog

7FFF6 AIE PWRIE ABE PIE RS3 RS2 RS1 RS0 Interrupts

7FFF5 ALM3 X 10-date alarm Alarm date 01–31 Alarm date

7FFF4 ALM2 X 10-hour alarm Alarm hours 00–23 Alarm hours

7FFF3 ALM1 Alarm 10 minutes Alarm minutes 00–59 Alarm minutes

7FFF2 ALM0 Alarm 10 seconds Alarm seconds 00–59 Alarm seconds

7FFF1 0.1 seconds 0.01 seconds 00–99 0.1/0.01 seconds

7FFF0 WDF AF PWRF BLF PF X X X Flags

Notes: X = Unused bits; can be written and read.

Clock/Calendar data in 24-hour BCD format.

BLF = 1 for low battery.

OSC = 1 stops the clock oscillator.

Interrupt enables are cleared on power-up.

Table 1. bq4842 Clock and Control Register Map

bq4852Y

Not Recommended For New Designs

Stopping and Starting the Clock Oscillator

The OSC bit in the seconds register turns the clock on or

off. If the bq4852Y is to spend a significant period of

time in storage, the clock oscillator can be turned off to

preserve battery capacity. OSC set to 1 stops the clock

oscillator. When OSC is reset to 0, the clock oscillator is

turned on and clock updates to user-accessible memory

locations occur within one second.

The OSC bit is set to 1 when shipped from the Bench-

marq factory.

Calibrating the Clock

The bq4852Y real-time clock is driven by a quartz con-

trolled oscillator with a nominal frequency of 32,768 Hz.

The quartz crystal is contained within the bq4852Y

package along with the battery. The clock accuracy of

the bq4852Y module is tested to be within 20ppm or

about 1 minute per month at 25°C. The oscillation rates

of crystals change with temperature as Figure 3 shows.

To compensate for the frequency shift, the bq4852Y of-

fers onboard software clock calibration. The user can

adjust the calibration based on the typical operating

temperature of individual applications.

The software calibration bits are located in the control

tion, and bit D5 the direction (positive or negative) of

correction. Assuming that the oscillator is running at

exactly 32,786 Hz, each calibration step of D0–D4 ad-

justs the clock rate by +4.068 ppm (+10.7 seconds per

month) or -2.034 ppm (-5.35 seconds per month) depend-

ing on the value of the sign bit D5. When the sign bit is

1, positive adjustment occurs; a 0 activates negative ad-

justment. The total range of clock calibration is +5.5 or

-2.75 minutes per month.

Two methods can be used to ascertain how much cali-

bration a given bq4852Y may require in a system. The

first involves simply setting the clock, letting it run for a

month, and then comparing the time to an accurate

known reference like WWV radio broadcasts. Based on

the variation to the standard, the end user can adjust

the clock to match the system’s environment even after

the product is packaged in a non-serviceable enclosure.

The only requirement is a utility that allows the end

user to access the calibration bits in the control register.

The second approach uses a bq4852Y test mode. When

the frequency test mode enable bit FTE in the days reg-

ister is set to a 1, and the oscillator is running at exactly

32,768 Hz, the LSB of the seconds register toggles at

512 Hz. Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of 512.01024 Hz

indicates a (1E6*0.01024)/512 or +20 ppm oscillator fre-

quency error, requiring ten steps of negative calibration

(10*-2.034 or -20.34) or 001010 to be loaded into the calibra-

Aug. 1996

Bits Description

ABE Alarm interrupt enable in

battery-backup mode

AF Alarm interrupt flag

AIE Alarm interrupt enable

ALM0–ALM3 Alarm repeat rate

BLF Battery-low flag

BM0–BM4 Watchdog multiplier

FTE Frequency test mode enable

OSC Oscillator stop

PF Periodic interrupt flag

PIE Periodic interrupt enable

PWRF Power-fail interrupt flag

PWRIE Power-fail interrupt enable

R Read clock enable

RS0–RS3 Periodic interrupt rate

S Calibration sign

W Write clock enable

WD0–WD1 Watchdog resolution

WDF Watchdog flag

WDS Watchdog steering

Table 2. Clock and Control Register Bits

Figure 3. Frequency Error

bq4852Y

Not Recommended For New Designs

tion byte for correction. To read the test frequency, the

bq4852Y must be selected and held in an extended read

of the seconds register, location 7FFF9, without having

the read bit set. The frequency appears on DQ0. The FTE

bit must be set using the write bit control. The FTE bit must

be reset to 0 for normal clock operation to resume.

Power-On Reset

The bq4852Y provides a power-on reset, which pulls the

RST pin low on power-down and remains low on power-

up for tCER after VCC passes VPFD.

Watchdog Timer

The watchdog circuit monitors the microprocessor’s ac-

tivity. If the processor does not reset the watchdog timer

within the programmed time-out period, the circuit as-

serts the INT or RST pin. The watchdog timer is acti-

vated by writing the desired time-out period into the

eight-bit watchdog register described in Table 3 (device

address 7FFF7). The five bits (BM4–BM0) store a bi-

nary multiplier, and the two lower-order bits

(WD1–WD0) select the resolution, where 00 = 116 second,

01 = 14second,10 = 1 second, and 11 = 4 seconds.

The time-out period is the multiplication of the five-bit

multiplier with the two-bit resolution. For example,

writing 00011 in BM4–BM0 and 10 in WD1–WD0 re-

sults in a total time-out setting of3x1or3seconds. A

multiplier of zero disables the watchdog circuit. Bit 7 of

the watchdog register (WDS) is the watchdog steering

bit. When WDS is set to a 1 and a time-out occurs, the

watchdog asserts a reset pulse for tCER on the RST pin.

During the reset pulse, the watchdog register is cleared to all

zeros disabling the watchdog. When WDS is set to a 0, the

watchdog asserts the INT pin on a time-out. The INT pin re-

mains low until the watchdog is reset by the microprocessor

or a power failure occurs. Additionally, when the watchdog

times out, the watchdog flag bit (WDF) in the flags register,

location 7FFF0,is set.

To reset the watchdog timer, the microprocessor must

write to the watchdog register. After being reset by a

write, the watchdog time-out period starts over. As a

precaution, the watchdog circuit is disabled on a power

failure. The user must, therefore, set the watchdog at

boot-up for activation.

Interrupts

The bq4852Y allows four individually selected interrupt

events to generate an interrupt request on the INT pin.

These four interrupt events are:

The watchdog timer interrupt, programmable to

occur according to the time-out period and conditions

described in the watchdog timer section

The periodic interrupt, programmable to occur once

every 122µs to 500ms.

The alarm interrupt, programmable to occur once per

second to once per month

The power-fail interrupt, which can be enabled to be

asserted when the bq4852Y detects a power failure

The periodic, alarm, and power-fail interrupts are en-

abled by an individual interrupt-enable bit in register

7FFF6, the interrupts register. When an event occurs,

its event flag bit in the flags register, location 7FFF0, is

set. If the corresponding event enable bit is also set,

then an interrupt request is generated. Reading the

flags register clears all flag bits and makes INT high im-

pedance. To reset the flag register, the bq4852Y ad-

dresses must be held stable at location 7FFF0 for at

least 50ns to avoid inadvertent resets.

Periodic Interrupt

Bits RS3–RS0 in the interrupts register program the

rate for the periodic interrupt. The user can interpret

the interrupt in two ways: either by polling the flags

goes active when the bq4852Y sets the periodic flag. Read-

ing the flags register resets the PF bit and returns INT to

the high-impedance state. Table 4 shows the periodic

rates.

Alarm Interrupt

Registers 7FFF5–7FFF2 program the real-time clock

alarm. During each update cycle, the bq4852Y com-

pares the date, hours, minutes, and seconds in the clock

registers with the corresponding alarm registers. If a

match between all the corresponding bytes is found, the

alarm flag AF in the flags register is set. If the alarm

interrupt is enabled with AIE, an interrupt request is

generated on INT. The alarm condition is cleared by a

MSB Bits LSB

76543210

WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0

Table 3. Watchdog Register Bits

Aug. 1996

bq4852Y

Not Recommended For New Designs

read to the flags register. ALM3–ALM0 puts the alarm

into a periodic mode of operation. Table 5 describes the

selectable rates.

The alarm interrupt can be made active while the

bq4852Y is in the battery-backup mode by setting ABE

in the interrupts register. Normally, the INT pin tri-

states during battery backup. With ABE set, however, INT

is driven low if an alarm condition occurs and the AIE bit is

set. Because the AIE bit is reset during power-on reset, an

alarm generated during power-on reset updates only the

flags register. The user can read the flags register during

boot-up to determine if an alarm was generated during

power-on reset.

Power-Fail Interrupt

When VCC falls to the power-fail-detect point, the power-

fail flag PWRF is set. If the power-fail interrupt enable bit

(PWRIE) is also set, then INT is asserted low. The power-

fail interrupt occurs tWPT before the bq4852Y generates a

reset and deselects. The PWIE bit is cleared on power-up.

Battery-Low Warning

The bq4852Y checks the internal battery on power-up.

If the battery voltage is below 2.2V, the battery-low flag

BLF in the flags register is set to a 1 indicating that

clock and RAM data may be invalid.

ALM3 ALM2 ALM1 ALM0 Alarm Frequency

1111Once per second

1110Once per minute when seconds match

1100Once per hour when minutes, and seconds match

1000Once per day when hours,minutes, and seconds match

0000When date, hours, minutes, and seconds match

Table 5. Alarm Frequency (Alarm Bits DQ7 of Alarm Registers)

RS3 RS2 RS1 RS0 Interrupt Rate

0000None

000110ms

0010100ms

0011122.07µs

0100244.14µs

0101488.281

0110976.5625

01111.953125ms

10003.90625ms

10017.8125ms

101015.625ms

101131.25ms

110062.5ms

1101125ms

1110250ms

1111500ms

Table 4. Periodic Rates

Aug. 1996

bq4852Y

Not Recommended For New Designs

Aug. 1996

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V

VTDC voltage applied on any pin excluding VCC

relative to VSS -0.3 to 7.0 V VT≤VCC + 0.3

TOPR Operating temperature 0 to +70 °C

TSTG Storage temperature (VCC off; oscillator off) -40 to +70 °C

TBIAS Temperature under bias -10 to +70 °C

TSOLDER Soldering temperature +260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.Functional operation

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-

ditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (TA=T

OPR)

Symbol Parameter Minimum Typical Maximum Unit Notes

VCC Supply voltage 4.5 5.0 5.5 V

VSS Supply voltage 0 0 0 V

VIL Input low voltage -0.3 - 0.8 V

VIH Input high voltage 2.2 - VCC + 0.3 V

Note: Typical values indicate operation at TA= 25°C.

bq4852Y

Not Recommended For New Designs

Aug. 1996

DC Electrical Characteristics (TA=T

OPR, VCCMIN ≤VCC ≤VCCMAX)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILI Input leakage current - - ±1µAV

IN =V

SS to VCC

ILO Output leakage current - - ±1µACE =V

IH or OE =V

IH or

WE =V

VOH Output high voltage 2.4 - - V IOH = -1.0 mA

VOL Output low voltage - - 0.4 V IOL = 2.1 mA

IOD RST, INT sink current 10 - - mA VOL = 0.4V

ISB1 Standby supply current - 3 6 mA CE =V

ISB2 Standby supply current - 2 4 mA CE ≥VCC - 0.2V,

0V ≤VIN ≤0.2V,

or VIN ≥VCC - 0.2V

ICC Operating supply current - - 90 mA Min. cycle, duty = 100%,

CE =V

IL,I

I/O = 0mA

VPFD Power-fail-detect voltage 4.30 4.37 4.50 V

VSO Supply switch-over voltage - 3 - V

Notes: Typical values indicate operation at TA= 25°C, VCC =5V.

RST and INT are open-drain outputs.

Capacitance (TA= 25°C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CI/O Input/output capacitance - - 10 pF Output voltage = 0V

CIN Input capacitance - - 10 pF Input voltage = 0V

Note: These parameters are sampled and not 100% tested.

bq4852Y

Not Recommended For New Designs

Aug. 1996

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0V to 3.0V

Input rise and fall times 5 ns

Input and output timing reference levels 1.5 V (unless otherwise specified)

Output load (including scope and jig) See Figures 4 and 5

Figure 5. Output Load BFigure 4. Output Load A

Read Cycle (TA=T

OPR, VCCMIN ≤VCC ≤VCCMAX)

Symbol Parameter

-85

Unit Conditions

Min. Max.

tRC Read cycle time 85 - ns

tAA Address access time - 85 ns Output load A

tACE Chip enable access time - 85 ns Output load A

tOE Output enable to output valid - 45 ns Output load A

tCLZ Chip enable to output in low Z 5 - ns Output load B

tOLZ Output enable to output in low Z 0 - ns Output load B

tCHZ Chip disable to output in high Z 0 35 ns Output load B

tOHZ Output disable to output in high Z 0 25 ns Output load B

tOH Output hold from address change 10 - ns Output load A

bq4852Y

Not Recommended For New Designs

Aug. 1996

Read Cycle No. 2 (CE Access) 1,3,4

Read Cycle No. 1 (Address Access) 1,2

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE =OE=V

IL.

3. Address is valid prior to or coincident with CE transition low.

4. OE =V

IL.

5. Device is continuously selected: CE =V

IL.

Read Cycle No. 3 (OE Access) 1,5

bq4852Y

Not Recommended For New Designs

Aug. 1996

Write Cycle (TA=TOPR , VCCMIN ≤VCC ≤VCCMAX)

Symbol Parameter

-85

Units Conditions/Notes

Min. Max.

tWC Write cycle time 85 - ns

tCW Chip enable to end of write 75 - ns (1)

tAW Address valid to end of write 75 - ns (1)

tAS Address setup time 0 - ns Measured from address valid to begin-

ning of write. (2)

tWP Write pulse width 65 - ns Measured from beginning of write to

end of write. (1)

tWR1 Write recovery time (write cycle 1) 5 - ns Measured from WE going high to end

of write cycle. (3)

tWR2 Write recovery time (write cycle 2) 15 - ns Measured from CE going high to end of

write cycle. (3)

tDW Data valid to end of write 35 - ns Measured to first low-to-high transi-

tion of either CE or WE.

tDH1 Data hold time (write cycle 1) 0 - ns Measured from WE going high to end

of write cycle. (4)

tDH2 Data hold time (write cycle 2) 10 - ns Measured from CE going high to end of

write cycle. (4)

tWZ Write enabled to output in high Z 0 30 ns I/O pins are in output state. (5)

tOW Output active from end of write 0 - ns I/O pins are in output state. (5)

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.

2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition

of CE going low and WE going low.

3. Either tWR1 or tWR2 must be met.

4. Either tDH1 or tDH2 must be met.

5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in

high-impedance state.

bq4852Y

Not Recommended For New Designs

Aug. 1996

Write Cycle No. 1 (WE-Controlled) 1,2,3

Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5

Notes: 1. CE or WE must be high during address transition.

2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the

outputs must not be applied.

3. If OE is high, the I/O pins remain in a state of high impedance.

4. Either tWR1 or tWR2 must be met.

5. Either tDH1 or tDH2 must be met.

bq4852Y

Not Recommended For New Designs

Aug. 1996

Power-Down/Power-Up Timing

Power-Down/Power-Up Cycle (TA=T

OPR)

Symbol Parameter Minimum Typical Maximum Unit Conditions

tPF VCC slew, 4.50 to 4.20 V 300 - - µs

tFS VCC slew, 4.20 to VSO 10 - - µs

tPU VCC slew, VSO to VPFD

(max.) 0--

CER Chip enable recovery time 40 100 200 ms Time during which SRAM is

write-protected after VCC

passes VFPD on power-up.

tDR Data-retention time in

absence of VCC 10 - - years TA= 25°C. (2)

tWPT Write-protect time 40 100 160 µsDelay after VCC slews down

past VPFD before SRAM is

write-protected.

Notes: 1. Typical values indicate operation at TA= 25°C, VCC =5V.

2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the

accumulated time in absence of power beginning when power is first applied to the device.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Notes: 1. PWRIE is set to “1” to enable power fail interrupt.

2. RST and INT are open drain and require an external pull-up resistor.

bq4852Y

Not Recommended For New Designs

bq4852Y

May 1997

MC: 36-Pin C-Type Module

36-Pin MC (C-Type Module)

Dimension

Inches Millimeters

Min. Max. Min. Max.

A 0.365 0.375 9.27 9.53

A1 0.015 - 0.38 -

B 0.017 0.023 0.43 0.58

C 0.008 0.013 0.20 0.33

D 2.070 2.100 52.58 53.34

E 0.710 0.740 18.03 18.80

e 0.590 0.630 14.99 16.00

G 0.090 0.110 2.29 2.79

L 0.120 0.150 3.05 3.81

S 0.175 0.210 4.45 5.33

bq4852Y MC -

Speed Options:

85=85ns

Package Option:

MC = C-type module

Device:

bq4852Y 512K x 8 Real-Time Clock Module

Ordering Information

Not Recommended For New Designs

PACKAGE OPTION ADDENDUM

www.ti.com 2-Apr-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

BQ4852YMC-85 NRND DIP MODULE MC 36 10 Pb-Free (RoHS) Call TI N / A for Pkg Type

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MECHANICAL DATA

MPDI063 – MAY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MC (R-PDIP-T36) PLASTIC DUAL-IN-LINE

0.110

0.150

0.023

0.013

0.375

0.630

2.100

0.740

Max.

0.710

0.090

0.120

0.590

2.070

0.017

–

Dimension

0.015

Min.

Inches

2.79

3.81

16.00

0.58

18.80

53.34

0.33

18.03

2.29

3.05

14.99

–

0.43

52.58

Millimeters

Max.

9.53

Min.

0.38

4201977/A 03/01

0.175

S0.210 4.45 5.33

0.365 9.27

0.008 0.20

NOTES: A. All linear dimensions are in inches (mm).

B. This drawing is subject to change without notice.

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