IR3710MTRPBF
Page 1 of 20 www.irf.com IR Confidential 4/26/10
WIDE INPUT AND OUTPUT, SYNCHRONOUS BUCK REGULATOR
FEATURES
Input Voltage Range: 3V to 28V
Output Voltage Range: 0.5V to 12V
Constant On-Time control
Excellent Efficiency at very low output current levels
Gate drive charge pump option to maximize
efficiency at higher output current levels
Compensation Loop not Required
Programmable switching frequency, soft start, and
over current protection
Power Good Output
Precision Voltage Reference (0.5V, +/-1%)
Enable Input with Voltage Monitoring Capability
Pre-bias Start Up
Under/Over Voltage Fault Protection
16pin 3x3 MLPQ lead free package
RoHS compliant
DESCRIPTION
The IR3710 is a single-phase sync-buck PWM
controller optimized for efficiency in high performance
portable electronics. The switching modulator uses
constant on-time control. Constant on-time with diode
emulation provides the highest light-load efficiency
required for all.
Programmable switching frequency, soft start, and over
current protection allows for a very flexible solution
suitable for many different applications. The
combination of the gate drive charge pump option and
constant on time control allow efficiency optimization in
the whole output current range, making this device an
ideal choice for battery powered applications.
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut down,
power good output, and enable input with voltage
monitoring capability.
APPLICATION CIRCUIT
Enhanced Gate Drive Application Circuit:
IR3710
BOOT
UGATE
PHASE
LGATE
EN
FB
PVCC
PGND
FF
ISET
VCC
GND
SS
FCCM
PGOOD
CPO
V5
V3.3
D1
D2
C1 RFF
RISET
CSS
CBOOT
COUT
L
R1
R2
DBOOT
VIN
VOUT
10k6.2k
ORDERING INFORMATION
Package Description Pin Count Parts Per Reel
IR3710MTRPbF 16 4000
Data Sheet No. PD60367
IR3710MTRPBF
Page 2 of 20 www.irf.com IR Confidential 4/26/10
Fix Gate Voltage Application Circuit:
IR3710
BOOT
UGATE
PHASE
LGATE
EN
FB
PVCC
PGND
FF
ISET
VCC
GND
SS
FCCM
PGOOD
CPO
V5
V3.3 RFF
RISET
CSS
CBOOT
COUT
L
R1
R2
DBOOT
VIN
VOUT
10k6.2k
NC
3.3V Input Voltage Application Circuit:
VOUT
IR3710
BOOT
UGATE
PHASE
LGATE
EN
FB
PVCC
PGND
FF
ISET
VCC
GND
SS
FCCM
PGOOD
CPO
V3.3
RFF
RISET
CSS
CBOOT
COUT
L
R1
R2
DBOOT
NC
10k6.2k
IR3710MTRPBF
Page 3 of 20 www.irf.com IR Confidential 4/26/10
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings (Referenced to GND)
BOOT Voltage: ................................................40 V
PHASE Voltage:....-5V(100ns),-0.3V(DC) to 32.5 V
FF, ISET:..........................................................32 V
BOOT minus PHASE Voltage:........................7.5 V
PVCC: ............................................................7.5 V
VCC:................................................................3.9 V
PGOOD:..........................................................3.9 V
PGND to GND:................................... -0.3V to 0.3V
All other pins ...................................................3.9 V
Operating Junction Temperature.. -10°C to +150oC
Storage Temperature Range .......... -65oC to 150oC
ESD Rating ...............................................Class 1C
MSL Rating ..................................................Level 2
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol Definition Min Max Units
VIN Input Voltage 3 28* V
BOOT to PHASE Supply Voltage 7.0 V
VOUT Output Voltage 0.5 12 V
Fs Switching Frequency 1000 kHz
* Note: PHASE pin must not exceed 32.5V.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply: VCC = 3.3V, PVCC = 7.0V, 0oC TJ 125oC
PARAMETER NOTE TEST CONDITION MIN TYP MAX UNIT
BIAS SUPPLIES
VCC Turn-on Threshold 3 V
VCC Turn-off Threshold 2.65 V
VCC Threshold Hysterisis 60 mV
PVCC Turn-on Threshold 3.05 V
PVCC Turn-off Threshold 2.65 V
PVCC Threshold Hysterisis 60 mV
VCC Shutdown Current EN=LOW 25 μA
VCC Operating Current EN=HIGH, No gate loading 1.2 mA
PVCC Shutdown Current EN=LOW; PVCC = 5V 20 μA
FF Shutdown Current EN=LOW 2 μA
CONTROL LOOP
Reference Accuracy, VREF V
FB = 0.5V 0.495 0.5 0.505 V
On-Time Accuracy RFF = 180K, VIN = 12.6V 270 300 330 ns
Zero Current Threshold Measure at VPHASE -4.5 4.5 mV
Soft-Start Current FCCM = EN = HIGH 8 10 12 μA
IR3710MTRPBF
Page 4 of 20 www.irf.com IR Confidential 4/26/10
NOTES:
1. Guaranteed by design, not tested in production
PARAMETER NOTE TEST CONDITION MIN TYP MAX UNIT
FAULT PROTECTION
ISET pin output current 18 20 22 μA
Under Voltage Threshold Falling VFB & monitor PGOOD 0.37 0.4 0.43 V
Under Voltage Hysteresis Rising VFB 7.5 mV
Over Voltage Threshold Rising VFB & monitor PGOOD 0.6 V
PGOOD Delay Threshold (VSS) 0.6 V
GATE DRIVE
UGATE Source Resistance 1 IGATE = 0.1A 1.5 3
UGATE Sink Resistance 1 IGATE = 0.1A 1 2
UGATE Rise and Fall Time 3nF load; 1V & 4V thresholds 10 ns
LGATE Source Resistance 1 IGATE = 0.1A 1.5 3
LGATE Sink Resistance 1 IGATE = 0.1A 0.4 1
LGATE Rise Time 6.8nF load; 1V to 4V 15 ns
LGATE Fall Time 6.8nF load; 4V to 1V 10 ns
Dead time Measure time from
VLGATE = 1V to VUGATE = 1V
5 50 ns
Minimum LGATE Interval 400 ns
CHARGE PUMP OUTPUT
Source Resistance ICPO =15mA 3.3 5
Sink Resistance ICPO =15mA 1 2.1
Charge Pump Disable
Threshold, VCP TH
FCCM = HIGH 6.8 7.2 V
LOGIC INPUT AND OUTPUT
EN Rising Threshold 1.14 1.22 1.3 V
EN Hysterisis 40 100 160 mV
EN Input Current 1 μA
FCCM Rising Threshold 1 1.2 V
FCCM Falling Threshold 0.5 0.7 V
FCCM Hysterisis 0.3
FCCM Input Current 1 μA
PGOOD pull down resistance IPGOOD =2mA 50 100
IR3710MTRPBF
Page 5 of 20 www.irf.com IR Confidential 4/26/10
IC PIN ORDER AND DESCRIPTION
NAME NUMBER I/O LEVEL DESCRIPTION
BOOT 1
VIN +PVCC Bootstrapped gate drive supply – connect a capacitor to PHASE
FF 2
VIN Input voltage feed forward – sets on-time with a resistor to VIN
EN 3 3.3V Enable input; EN = LOW inhibits GATE pulses
ISET 4 32V Current limit setting with a resistor to PH pin
PGOOD 5 3.3V Power good – pull up to 3.3V
GND 6
Reference Bias return and signal reference
FCCM 7 3.3V Force continuous conduction mode when pulled up to VCC
FB 8 3.3V Feedback input
SS 9 3.3V Set soft start slew-rate with a capacitor to GND
VCC 10 3.3V IC bias supply
CPO 11 3.3V Charge Pump Output
PVCC 12 7.4V Gate drive supply
LGATE 13 PVCC Lower gate drive for synchronous MOSFET
PGND 14 Reference Power return – connect to source of synchronous MOSFET
PHASE 15 VIN Phase node (or switching node) of MOSFET half bridge
UGATE 16
VIN + V5 Upper gate drive for control MOSFET
UGATE
PHASE
PGND
LGATE
EN
BOOT
FF
PVCC
CPO
VCC
GND FB
ISET SS
FCCMPGOOD
1
2
3
4
5
6
7
8
12
11
10
9
16
15
14
13
GND
JA = 49 oC/W
JC = 4 oC/W
IR3710MTRPBF
Page 6 of 20 www.irf.com IR Confidential 4/26/10
BLOCK DIAGRAM
SSDelay
PWM
BOOT
UGATE
PHASE
LGATE
GATE
DRIVE
LOGIC
PGND
ON-TIME
FF
+
-
SOFT
START
SS
Run
+
EN
PGOOD
FB
VCC
GND
ISET
FCCM
CONTROL
LOGIC
POR
+
-
VREF
x0.8
OVER
CURRENT
OC#
FF
x1.2
UV#
CPO
VCC
VCC
PGND
PVCC
FCCMFF
VCC
PVCC
PWM
COMP SET
PVCC
Charge
Pump
Regulator
ZCROSS
Run
+
-
OV
PVCC
Run
DCM
ZCROSS
IR3710MTRPBF
Page 7 of 20 www.irf.com IR Confidential 4/26/10
TYPICAL OPERATING DATA
(Circuit of Figure 18, VCC = 3.3V, V5 = 5V, VIN = 12.6V, Unless otherwise noted.)
Figure 1. Feedforward Resistance vs Switching Freq:
0.5V VOUT step, FCCM = HIGH.
0
50
100
150
200
250
300
350
0 2 4 6 8 10 12 14 16 18 20 22 24
Output Current (A)
Switching Frequency (KH
z
Freq vs Load
Figure 2. Switching Frequency vs Output Current
1.09800
1.09850
1.09900
1.09950
1.10000
1.10050
1.10100
1.10150
0 2 4 6 8 1012141618202224
Output Current(A)
Vout(V
)
12Vin@0C 12Vin@65C 19Vin@0C 19Vin@65C
Figure 3. Output Voltage Regulation versus Input
Voltage and Ambient Temperature
76
78
80
82
84
86
88
90
0 2 4 6 8 10 12 14 16 18 20 22 24
Output Current(A)
Efficiency (%
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Power Loss (W)
19Vin 12Vin Ploss-19Vin Ploss-12Vin
Figure 4. System Efficiency
6
6.2
6.4
6.6
6.8
7
7.2
7.4
0 5 10 15 20 25 30 35 40 45
Gate Charge (nC)
PVCC (V
)
Fs =300kHz; Ccpo=1uF Fs=1.34MHz ;Ccpo=1uF
Figure 5. Charge Pump Regulation
78
80
82
84
86
88
90
0 2 4 6 8 10 12
Output Current(A)
Efficiency (
%
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Power Loss (
W)
5V Drive Enhanced Gate
Ploss-5V Drive Ploss-Enhanced Gate
Figure 6. Charge Pump Efficiency Comparison:
1.25Vout, 12.6Vin, 300kHz,
IRF8721/8721, 0.82uH (4.2mOhm DCR)
Switching Frequency
Feedforward Resistance
1000000
000000
Rff 0.5 fsw,()
Rff 1 fsw,()
Rff 1.5 fsw,()
Rff 2 fsw,()
Rff 2.5 fsw,()
Rff 3 fsw,()
Rff 3.5 fsw,()
Rff 4 fsw,()
Rff 4.5 fsw,()
Rff 5 fsw,()
1000000200000 fsw
Switching Frequency (KHz)
Feedforward Resistance (K)
200 1000
0
1000
V
OUT
= 0.5V
V
OUT
= 5V
Switching Frequency
Feedforward Resistance
1000000
000000
Rff 0.5 fsw,()
Rff 1 fsw,()
Rff 1.5 fsw,()
Rff 2 fsw,()
Rff 2.5 fsw,()
Rff 3 fsw,()
Rff 3.5 fsw,()
Rff 4 fsw,()
Rff 4.5 fsw,()
Rff 5 fsw,()
1000000200000 fsw
Switching Frequency (KHz)
Feedforward Resistance (K)
200 1000
0
1000
V
OUT
= 0.5V
V
OUT
= 5V
IR3710MTRPBF
Page 8 of 20 www.irf.com IR Confidential 4/26/10
TYPICAL OPERATING WAVEFORM
(Circuit of Figure 18, VCC = 3.3V, V5 = 5V, VIN = 12.6V, Unless otherwise noted.)
CH1:Vout(0.5V/div), CH2: PHASE (20V/div)
CH3: PGOOD(5V/div), CH4:EN(5V/div) ; 50uS/div
Figure 7. Start up with FCCM = Low @ 30mA
CH1:Vout(0.5V/div), CH2: PHASE (20V/div)
CH3: PGOOD(5V/div), CH4:EN(5V/div) ; 50uS/div
Figure 8. Start up with Prebias Vout, FCCM = Low @ 30mA
CH1:Vout(20mV/div), CH2: PHASE (5V/div), CH4:
CPO(2V/div) ; 100uS/div
Figure 9. Charge Pump Off in DCM
CH1:Vout(20mV/div), CH2: PHASE (5V/div)
CH4: CPO(2V/div) ; 5uS/div
Figure 10. Charge Pump ON
CH1:Vout(20mV/div), CH2: PHASE (5V/div)
CH4: FCCM(5V/div) ; 100uS/div
Figure 11. DCM/FCCM Transition
IR3710MTRPBF
Page 9 of 20 www.irf.com IR Confidential 4/26/10
CH1:Vout(50mV/div), CH2: PHASE (5V/div);50uS/div
Figure 12. Frequency Variation less than 10% at 20A Load
CH1:Vout(50mV/div), CH3: Inductor Current (10A/div),
CH4: On-Board Load: 0A-14A ;50uS/div
Figure 13. Load Step Transient in CCM @ Vin = 19V
CH1:Vout(50mV/div), CH3: Inductor Current (10A/div),
CH4: On-Board Load: 0.1A-12A; 50uS/div
Figure 14. Load Step Transient in DCM @ Vin = 19V
CH2:Vout(20mV/div), CH3: Input Current (10A/div), CH4:
Input Voltage (5V/div) 8V to 19V; 100uS/div
Figure 15. Input Voltage Step at 2A Load with 0.1V/uS
CH1:Vout(0.5V/div), CH2: PHASE (10V/div), CH3: FB
(0.5V/div), CH4: PGOOD (5V/div); 500uS/div
Figure 16. Over Current Protection at 30A
CH1:Vout(0.5V/div), CH2: PHASE (10V/div), CH3: EN
(5V/div), CH4: PGOOD (2V/div); 200uS/div
Figure 17. Shutdown by EN in DCM @500mA
IR3710MTRPBF
Page 10 of 20 www.irf.com IR Confidential 4/26/10
TYPICAL OPERATING CIRCUIT
IR3710
BOOT
UGATE
PHASE
LGATE
EN
FB
PVCC
PGND
FF
ISET
VCC
GND
SS
FCCM
PGOOD
CPO
V5
V3.3
D1
D2
1uF
5.11K
2.2nF
2x330uF
(9mOHM)
L
1.96K
1.65K
VIN
0.5uH
(0.82mOhm)
56pF
BAT54S BAT54T
0.1uF
180K
IRF6721
IRF6635
Vout = 1.1V
2x10uF
Figure 18. Typical Application Circuit for 24A Load
IR3710MTRPBF
Page 11 of 20 www.irf.com IR Confidential 4/26/10
FUNCTIONAL DESCRIPTION
Refer to Block Diagram
ON-TIME GENERATOR
The PWM comparator initiates a SET signal (PWM
pulse) when the FB pin falls below lower of the
reference (VREF) or soft start (SS) voltage.
The PWM on-time duration is programmed with an
external resistor (RFF) from the input supply (VIN) to
the FF pin. The simplified equation for RFF is shown
in the equation 1. The FF pin is held to an internal
reference after EN goes HIGH. A copy of the current
in RFF charges a timing capacitor, which set the on-
time duration, as shown in equation 2.
(1)
F201
V
RSW
OUT
FF ⋅⋅
=pFV
(2)
V
201R
TIN
FF
ON pFV ⋅⋅
=
SOFT START
An internal 10uA current source charges external
capacitor on the SS pin to set the output voltage slew
rate during the soft start interval. The output voltage
reaches regulation when the FB pin is above the
under voltage threshold and the UV# = HIGH. Once
the voltage on the SS pin is above the PGOOD delay
threshold, the combination of the SSDelay and UV#
signals release the PGOOD pin. With EN = LOW, the
capacitor voltage and SS pin is held to the FB pin
voltage.
OVER CURRENT MONITOR
IR3710 monitors the output current every switching
cycle. The voltage across the synchronous
MOSFET, VPHASE is monitored for over current and
zero crossing. The minimum LGATE interval allows
time to sample VPHASE.
The over current trip point is programmed with a
resistor from ISET to PHASE pins, as shown in
equation 3. When over current is detected, output
gates are tri-state and SS voltage is pulled to 0V. A
new soft start cycle begins right after. If there is three
(3) consecutive OC events, IR3710 will disable
switching. Toggling VCC or EN will allow next start
up.
(3)
20
IR
ROC DSON
SET A
μ
⋅
=
GATE DRIVE LOGIC
The gate drive logic features adaptive dead time,
diode emulation, and a minimum lower gate interval.
An adaptive dead time prevents the simultaneous
conduction of the upper and lower MOSFETs. The
lower gate voltage must be below approximately 1V
after PWM goes HIGH before the upper MOSFET
can be gated on. Also the upper gate voltage, the
difference voltage between UGATE and PHASE,
must be below approximately 1V after PWM goes
LOW and before the lower MOSFET can be gated
on.
Diode emulation is enabled after PGOOD = HIGH
when FCCM is LOW. The control MOSFET is gated
on after the adaptive delay for PWM = HIGH and the
synchronous MOSFET is gated on after the adaptive
delay for PWM = LOW. The lower MOSFET is driven
‘off’ when the signal ZCROSS indicates that the inductor
current reverses as detected by the PHASE voltage
crossing the zero current threshold. The synchronous
MOSFET stays ‘off’ until the next PWM falling edge.
When FCCM = HIGH, forced continuous current
condition is selected. The control MOSFET is gated
on after the adaptive delay for PWM = HIGH and the
synchronous MOSFET is gated on after the adaptive
delay for PWM = LOW.
The synchronous MOSFET gate is driven on for a
minimum duration. This minimum duration allows
time to recharge the bootstrap capacitor and allows
the current monitor to sample the phase voltage.
CONTROL LOGIC
The control logic monitors input power sources for
supply voltage conditions, sequences the converter
through the soft-start and protective modes, and
indicates output voltage status on the PGOOD pin.
VCC and PVCC pins are continuously monitored.
IR3710 is disabled if either of these voltages drops
below falling thresholds.
IR3710 will initiate a soft start when the VCC and
PVCC are in the normal range and the EN pin =
HIGH. In the event of a sustained overload, a
counter keep track of 4 consecutive soft-start cycles
and disables IR3710.
If the overload is momentary and output voltage is
within regulation before 4 consecutive soft-start
cycles, PGOOD transitions HIGH to reset the
counter.
OVER VOLTAGE PROTECTION
IR3710 monitors the voltage at FB node. If the FB
voltage is above the threshold of over voltage, the
gates are turn off and pulls PGOOD signal low.
Toggling VCC or EN will allow next start up.
IR3710MTRPBF
Page 12 of 20 www.irf.com IR Confidential 4/26/10
CHARGE PUMP
The purpose of the charge pump is to improve the
system efficiency. A combination of VCC, V5 and
three(3) external components are used to boost
PVCC up to VCP TH. PVCC drives the synchronous
MOSFET and reduces the RDSON when compared to
a regular 5V rail driver. The lower RDSON reduces the
conduction power loss as discussed in the Power
Loss section.
The charge pump is continuously enabled for FCCM
= HIGH. The charge pump circuit is disabled when
FCCM = LOW and the output loading is less than half
of inductor current ripple. In this case, PVCC is two
(2) diode voltage away from V5 rail. Therefore, the
power loss for driver is reduced. The charge pump
circuit stops switching the CPO pin for PVCC above
VCP TH.
It is not recommended to use PVCC for supply power
to boot capacitor when use charge pump circuit. This
can be exceeding the maximum rating of BOOT to
PHASE pins and damages to the IC.
POWER UP SEQUENCE
With EN pin HIGH, IR3710 initiates a soft start when
the VCC and PVCC are in the above ULVO threshold
and VIN is in normal range. The order of VCC, PVCC
and VIN is not require.
COMPONENT SELECTION
Selection of components for the converter is an
iterative process which involves meeting the
specifications and trade-offs between the
performance and cost. The following sections will
guide one through the process.
Power Loss
The main sources contributing to the power loss of a
converter are switching loss of the upper MOSFETs,
conduction loss of the lower MOSFETs, AC and DC
losses in the inductor, and driving loss which is a
large factor at light load condition.
In small duty cycle converter system, switching loss
is main power loss of upper MOSFETs because its
on-time is relatively small. To find the switching
power loss, Figure 19 shows the typical turn-on
waveform of the upper MOSFETs. Turn-off is
quantitatively similar with x-axis reversed. The
switching loss can be estimate as the cross sectional
area in the figure. Equation 4 and 5 show the
relationship of MOSFET’s switching charge and loss.
()
(5) F
I
QQ IV
FWP
(4) t1-t3
IV
W
S
GDr
GD GS2
2
PK IN
SONSW
2
PK IN
ON
⋅⋅==
=
+⋅
⋅
⋅
Fs is the switching frequency. IGDr is gate driver
current. To find the driver current, Figure 20 shows
the simplified circuit of driver and MOSFET. IGdr can
be found by using Ohm’s law as shown in the
equation 6 with an assumption that VQgd is the gate
voltage during t2 and t3. Therefore, the turn on
switching power loss of a cycle can be easily be
found as shown in equation 7.
VGS(th)
VGS
IPK
VIN
t
QGS1
IOUT
t1t3
t2
QGS2 QGD
IGdr
Figure 19. Typical Turn-On Waveform.
VDR
VQgd
Driver MOSFET
RPU
RG
REXT
CGS
CGD
CDS
RPD
Figure 20. Simplify Driver and MOSFET Circuit.
(7) F
I
QQ IV
P
(6b)
RRR
V
I
(6a)
RRR
VV
I
S
time)-GDr(on
GD GS2
2
PK IN
SW
G EXT PD
Qgd
time)-GDr(off
G EXT PU
Qgd -DR
time)-GDr(on
⋅⋅=
=
=
+⋅
++
++
The reverse recovery power loss of the lower
MOSFETs is also a factor of the upper MOSFET’s
IR3710MTRPBF
Page 13 of 20 www.irf.com IR Confidential 4/26/10
switching power loss because the output current flow
through the lower MOSFET’s body diode during the
dead time stores some minority charges. When the
upper MOSFETs turn on, it has to carry this extra
current to remove the minority charges. The reverse
recovery power loss can be found in equation 8.
(8) SINrrQrr FVQP ⋅⋅=
By combining the PSW and PQrr, the total switching
power loss of the upper MOSFETs is much greater
than its conduction loss. International Rectifier
MOSFET datasheets has separated the gate charge
of QGS1 and QGS2 so that the designer can calculate
the switching power loss. Therefore, selection of the
upper MOSFETs should consider those factors.
Otherwise, the converter losses degrade the system
efficiency and may exceed the thermal constraints.
The main power loss of lower MOSFETs is the
conduction loss because its on-time is in the range of
90% of the switching period. The switching power
loss of lower MOSFETs can be negligible because
their body diode voltage drops are in the range of 1V.
Equation 9 shows the conduction power loss
calculation. TS is inversely proportional to fs, and TOFF
is the on-time of the lower MOSFETs. RDS(on)
increases approximately 30% with temperature.
2
OUT
OUT RMS_COND
OFF
DSON
2
RMS_CONDCOND
I
ΔI
3
1
1D-1I I :Where
(9)
Ts
T
RIP
⎟
⎠
⎞
⎜
⎝
⎛
⋅+⋅⋅=
=⋅⋅
The driver power loss is a small factor when heavily
loaded but it can be significant contributor of
degradation to the converter efficiency in light load.
Equation 10 shows the driver power loss relating to
the total gate charge of upper and lower MOSFETs
and switching frequency.
(10) FQ Vdt I V
Ts
1
P S GTotalDRGDr
Ts
0
DR
COND ⋅⋅⋅ ⋅== ∫
The low frequency and core losses are main factors
of the total power loss of an inductor. Low frequency
loss of an inductor is caused by the resistance of
copper winding. The copper loss of the winding is
shown in equation 11. The core loss of an inductor
depends on the B-H loop characteristic, volume and
frequency. This data can be obtained from the
inductor manufactures.
2
⎟
⎠
⎞
⎜
⎝
⎛
⋅+⋅
⋅
=
=
OUT
ΔI
3
1
1OUT RMS
2
RMSDCR
I
II :Where
(11)DCR IP
Inductor Selection
Inductor selection involves meeting the steady state
output ripple requirement, minimizing the switching
loss of upper MOSFETs, transient response and
minimizing the output capacitance. The output
voltage includes a DC voltage and a small AC ripple
component due to the low pass filter which has
incomplete attenuation of the switching harmonics.
Neglecting the inductance in series with output
capacitor, the magnitude of the AC voltage ripple is
determined by the total inductor ripple current flow
through the total equivalent series resistance (ESR)
of the output capacitor bank.
() ()
(12)
FLV
VVV
TsD1
L
V
ΔIsIN
OUTINOUTOUT
⋅
⋅
=⋅−⋅= ⋅
−
One can use equation 12 to find the inductance. The
main advantage of small inductance is increased
inductor current slew rate during a load transient,
which leads to small output capacitance requirement
as discussed in the Output Capacitor Selection
section. The draw back of using smaller inductances
is increased switching power loss in upper
MOSFETs, which reduces the system efficiency and
increases the thermal dissipation as discussed in the
Power Loss section.
Input Capacitor Selection
The main function of the input capacitor bank is to
provide the input ripple current and fast slew rate
current during the load current step up. The input
capacitor bank must have adequate to handle the
total RMS current. Figure 21 shows a typical input
current. Equation 13 shows the RMS input current.
The RMS input current contains the DC load current
and the inductor ripple current. As shown in equation
12, inductor ripple current is unrelated to the load
current. The maximum RMS input current occurs at
the maximum output current. The maximum power
dissipate in the input capacitor equals the square of
the maximum RMS input current times the input
capacitor’s total ESR.
Figure 21. Typical Input Current Waveform.
()
(13)
I
ΔI
3
1
1DIdttf
Ts
1
I
2
OUT
OUT
Ts
0
2
IN_RMS ⎟
⎠
⎞
⎜
⎝
⎛
⋅+⋅⋅=⋅⋅= ∫
IR3710MTRPBF
Page 14 of 20 www.irf.com IR Confidential 4/26/10
The voltage rating of the input capacitor needs to be
greater than the maximum input voltage because of
the high frequency ringing at the phase node. The
typical percentage is 25%.
Output Capacitor Selection
Select the output capacitor involves meeting the
overshoot requirement during the load removal,
transient response when the system is demanding
the current and meeting the output ripple voltage
requirement. The output capacitor has the higher
cost in the converter and increases the overall
system cost. The output capacitor decoupling in the
converter typically includes the low frequency
capacitor, such as Specialty Polymer Aluminum, and
mid frequency ceramic capacitors.
The first purpose of output capacitors is to provide
the different energy when the load demands the
current until the inductor current reaches the load’s
current as shown in figure 22. Equation 14 shows
the charge requirement for certain load. The
advantage of IR3710 at the load step is to reduce the
delay, Tdmax, down to logic delay (in nanosecond)
compare to fix frequency control method in
microsecond or (1-D)*Ts. If the load increases right
after the PWM signal low, the longest delay of Tdmax
will be equal to the minimum lower gate on as shown
in Electrical Specification table. IR3710 also reduces
the total inductor time, which takes to reach output
current, by increasing the switching frequency up to
2.5MHz. The result reduces the recovery time.
Figure 22. Charge Requirement during Load Step
() ()
(14b)
VV
ΔIL
2
1
Fs
D1
ΔI
V
1
C
(14a)dt I0.5TIVC Q
OUTIN
2
OUT
OUT
DROP
OUT1
OUTdmaxOUT
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡⋅
⋅+
−
⋅=
⋅⋅+⋅=⋅=
−
The output voltage drops, VDROP, initially depending
on the characteristic of the output capacitor. VDROP is
the sum of equivalent series inductance (ESL) of
output capacitor times the rate of change output
current and ESR times the change of output current.
VESR is usually much greater than VESL. IR3710
requires a total ESR such that the ripple voltage at
the FB pin is 7mV.
The second purpose of the output capacitor is to
minimize the overshoot of the output voltage when
the load decreases as shown in Figure 23. By using
the law of energy before and after the load removal,
equation 15 shows the output capacitance
requirement for a load step.
(15)
VV
IL
C 2
OUT
2
OS
2
STEP
OUT2 −
⋅
=
Figure 23. Typical Output Voltage Response
Vaveform.
Boot Capacitor Selection
The boot capacitor starts the cycle fully charged to a
voltage of VB(0). An equivalent gate drive
capacitance is calculated by consulting the high side
MOSFET data sheet and taking the ratio of total gate
charge at the V5 voltage, QG(V5), to the V5 voltage.
QG(V5)/V5 is the equivalent gate drive capacitance
Cg which will be used in the following calculations.
The voltage of the capacitor pair CB and Cg after Cg
becomes charged at CB’s expense will be VB(0)-V.
Choose a sufficiently small V such that VB(0)-V
exceeds the maximum gate threshold voltage to turn
on the high side MOSFET. Since total charge QT is
conserved, we can write the following equations.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−⋅=
+⋅
=
=
⋅
1
ΔV
(0)V
CC
(16) )C(C)V(tQC(0)V
B
gB
gBonTBB
Choose a boot capacitor value larger than the
calculated CB. The voltage rating of this part needs to
be larger than VB(0) plus the desired derating
voltage. The voltage between BOOT and PHASE
pins must not exceed the maximum rating of IR3710.
Its ESR and ESL needs to be low in order to allow it
to deliver the large current and di/dt’s which drive
MOSFETs most efficiently. In support of these
requirements a ceramic capacitor should be chosen.
IR3710MTRPBF
Page 15 of 20 www.irf.com IR Confidential 4/26/10
DESIGN EXAMPLE
Design Criteria:
Input Voltage, VIN, = 6V to 21V
Output Voltage, VOUT = 1.1V
Switching Frequency, FS = 300KHz
Inductor Ripple Current, I = 5A
Maximum Output Current, IOUT = 20A
Over Current Trip, IOC = 30A
Overshoot Allowance, VOS = VOUT + 150mV
Undershoot Allowance, VDROP = 150mV
Find RFF :
K 183
300K201
1.1
RFF Ω=
⋅⋅
=HzpFV V
Pick 182K for 1% standard resistor
Find RSET :
Ω=
Ω⋅
=⋅5.85K
20
30 3m1.3
R
SET AA
μ
1.3 factor is base on RDSON of lower MOSFET
increase over the temperature. Therefore, pick 5.9K
for 1% standard resistor.
Find resistor divider for VOUT = 1.1V:
V0.5 V
RR
R
VOUT
12
2
FB =⋅
+
=
R2 = 8.45K, R1 = 10K for 1% standard resistor
Choose the soft start capacitor:
Once the soft start time has chosen such as 100uS to
reach to the reference voltage, a 2.2nF for CSS is
used to meet 100uS.
Choose inductor to meet design specification:
()()
H
HzAV VVV 0.7u
300K521
1.1-211.1
FΔIV
VVV
LsIN
OUTINOUT =
⋅⋅
⋅
=
⋅
⋅
=⋅
−
Choose the inductor with lowest DCR and AC power
loss as possible to increase the overall system
efficiency. For instance, choose FDUE1250-R56M
from TOKO manufacture. The inductance of this part
is 0.56uH and has 0.82m DCR. The core loss for
this inductor is 0.41W and 0.41W for DCR. Ripple
current needs to recalculate with a chosen inductor.
(
)
A
HzHV VVV 6.2
300K0.56u21
1.1-211.1
ΔI=
⋅⋅
⋅
=
Choose input capacitor:
A
A
A
V
V
A4.7
20
6.2
3
1
1
21
1.1
20I
2
IN_RMS =
⎟
⎠
⎞
⎜
⎝
⎛
⋅+⋅⋅=
A 10uF (ECJ3YB1E106M) from Panasonic
manufacture has 6Arms at 300KHz. Due to the
chemistry of multilayer ceramic capacitors, the
capacitance varies over temperature and operating
voltage both of AC and DC. Two (2) of 10uF are
recommended. In practical solution, one (1) of 1uF is
required along with 2x10uF. The purposes of 1uF are
to suppress the switching noise and deliver a high
frequency current.
Choose output capacitor:
To meet the undershoot specification, select a set of
output capacitor which has an equivalent of 7.5m
(150mV/20A). To meet the overshoot specification,
equation 15 will be use to calculate the minimum
output capacitance. As a result, 516uF will be
needed. Combine those two requirements, one can
choose a set of output capacitor bank from
manufactures such as SP-Cap (Specialty Polymer
Capacitor) from Panasonic or POSCAP from Sanyo.
Two (2) of 270uF (EEFUD0D271XR) from Panasonic
are recommended. This capacitor has 12m ESR
which leaves margin for voltage drop of ESL during
load step up. The typical ESL for this capacitor is
around 2nH.
LAYOUT RECOMMENDATION
Bypass Capacitor:
One 1uF high quality ceramic capacitor is
recommended to be placed as near VCC pin as
possible. Other end of capacitor can be via or directly
connect to GND plane. Use a GND plane not a thin
trace to GND pin because this thin trace has higher
impedance compare to GND plane. A 1uF is
recommended for both V5 and PVCC and repeat the
layout procedure above for those signals.
Charge Pump:
It is recommended to place D1, D2 and C2 as close
to the CPO and PVCC pins as possible. If those
components can not placed on the same layer as
IR3710, a minimum of two (2) vias need for the
connection of C2 and CPO pin and the connection of
D2 and PVCC.
Boot Circuit:
CBOOT needs to place near BOOT and PHASE pins to
reduce the impedance during the turn on of the upper
MOSFET. DBOOT does not need to be close to CBOOT
because the average current to charge CBOOT is small
during the on time of lower MOSFET.
IR3710MTRPBF
Page 16 of 20 www.irf.com IR Confidential 4/26/10
Gate Impedance:
We recommended placing LGATE signal path on top
next to the source of low side MOSFET path and
place UGATE signal path on top of PHASE signal
path.
If the connection of PGND pin to the source of low
side MOSFET is through an internal layer, it is
recommended connecting through at least 2 vias by
build a small island of next to PGND pin.
Power Stage:
Figure 24 shows the flowing current path for on and
off period. The on time path has low average DC
current with high AC current. Therefore, it is
recommended to place input ceramic capacitor,
upper and lower MOSFET in a tight loop as shown in
Figure 24. The purpose tight loop of input ceramic
capacitor is to suppress the high frequency (10MHz
range) switching noise to reduce Electromagnetic
Interference (EMI). If this path has high inductance,
the circuit will cause voltage spike and ringing,
increase the switching loss. The off time path has low
AC and high average DC current. Therefore, it is
recommended to layout with tight loop and fat trace
at two end of inductor. The higher resistance of this
loop increases the power loss. The typical resistance
value of 1 ounce copper thickness has one-half mili-
per square.
Figure 24. Current Path of Power Stage
IR3710MTRPBF
Page 17 of 20 www.irf.com IR Confidential 4/26/10
PCB PAD AND COMPONENT PLACEMENT
Figure 25. Ssuggested pad and component placement.
IR3710MTRPBF
Page 18 of 20 www.irf.com IR Confidential 4/26/10
SOLDER RESIST
Figure 26. Suggested solder resist placement.
IR3710MTRPBF
Page 19 of 20 www.irf.com IR Confidential 4/26/10
STENCIL DESIGN
Figure 27. Suggested stencil design.
IR3710MTRPBF
Page 20 of 20 www.irf.com IR Confidential 4/26/10
PACKAGE INFORMATION
Figure 28. Package Outline Drawing
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUATERS: 233 Kansas St, EL Segundo, California 90245, USA Tel: (310)-252-7105
TAC Fax: (310)-252-7903
Visit us at www.irf.com for sales contact information. www.irf.com
