1999 Microchip Technology Inc. DS30235H-page 1
Devices included in this data sheet:
Referred to collectively as PIC16C62X .
• PIC16C620 • PIC16C620A
• PIC16C621 • PIC16C621A
• PIC16C622 • PIC16C622A
• PIC16CR620A
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
• Interrupt capability
• 16 special function hardware registers
• 8-level deep hardware stack
• Direct, Indirect and Relative addressing modes
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two ana log comp arators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
prog r am ma ble presca le r
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Device Program
Memory Data
Memory
PIC16C620 512 80
PIC16C620A 512 96
PIC16CR620A 512 96
PIC16C621 1K 80
PIC16C621A 1K 96
PIC16C622 2K 128
PIC16C622A 2K 128
Pin Di agrams
Special Micr ocontroller Features (cont’d)
• Programmable code protection
• Pow er saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
• Four user programmable ID location s
CMOS Technology:
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range
- PIC16C62X - 2.5V to 6.0V
- PIC16C62XA - 2.5V to 5.5V
- PIC 16CR620A - 2.0V to 5.5V
• Commerc ial, in dustrial an d extende d temp eratu re
range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
-15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
RA1/AN1
RA0/AN0
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/VREF
RA3/AN3
MCLR/VPP
VSS
RB0/INT
RB1
RB2
RB3
RA4/T0CKI
PIC16C62X
RA1/AN1
RA0/AN0
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/VREF
RA3/AN3
MCLR/VPP
VSS
VSS
RB0/INT
RB1
RB2
RA4/T0CKI
RB3RB3
VDD
PDIP, SOIC, Windowed CERDIP
SSOP
2
3
4
5
6
7
8
9
10
•1
2
3
4
5
6
7
8
9
•1
19
18
16
15
14
13
12
11
17
18
17
15
14
13
12
11
10
16
20
PIC16C62X
EPROM-Based 8-Bit CMOS Microcontrollers
PIC16C62X
PIC16C62X
DS30235H-page 2 1999 Mic rochip Technology Inc.
Device Differences
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note 2: For ROM parts, operation from 2.0V - 2.5V will require the PIC16LCR62X parts.
Note 3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X parts.
Device Voltage
Range Oscillator Process
Technology
(Microns)
PIC16C620 2.5 - 6.0 See Note 1 0.9
PIC16C621 2.5 - 6.0 See Note 1 0.9
PIC16C622 2.5 - 6.0 See Note 1 0.9
PIC16C620A(3) 2.5 - 5.5 See Note 1 0.7
PIC16CR620A(2) 2.0 - 5.5 See Note 1 0.7
PIC16C621A(3) 2.5 - 5.5 See Note 1 0.7
PIC16C622A(3) 2.5 - 5.5 See Note 1 0.7
1999 Microchip Technology Inc. DS30235H-page 3
PIC16C62X
Table of Contents
1.0 General Description..............................................................................................................................................5
2.0 PIC16C62X Device Varieties...............................................................................................................................7
3.0 Architectural Overview..........................................................................................................................................9
4.0 Memory Organization..........................................................................................................................................13
5.0 I/O Ports..............................................................................................................................................................25
6.0 Timer0 Module....................................................................................................................................................31
7.0 Comparator Module............................................................................................................................................ 37
8.0 Voltage Reference Module .................................................................................................................................43
9.0 Special Features of the CPU ..............................................................................................................................45
10.0 Instruction Set Summary.....................................................................................................................................61
11.0 Development Support.........................................................................................................................................75
12.0 Electric al Specifi ca tio ns...................... ..... ...... ...... ..... ....................... ..... ....................... ... ....................................81
13.0 Device Characte riz ati on Infor mation.......................................... ...... ...................... ...... ...................... ...... .........101
14.0 Packaging Information ......................................................................................................................................105
Appendix A: Enhancements .....................................................................................................................................111
Appendix B: Compatibility.........................................................................................................................................111
Index...........................................................................................................................................................................113
On-Line Support..........................................................................................................................................................115
PIC16C62X Product Identification System ................................................................................................................ 117
To Our Valued Customers
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workarounds. As de vice/documentation issues become known to us , we wil l publish an errata sheet. The errat a will specify the re vi-
sion of silicon and re vision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and document ation. We h ave spent a great deal of time to ensure
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We appreciate your assistance in making this a better document.
PIC16C62X
DS30235H-page 4 1999 Mic rochip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 5
PIC16C62X
1.0 GENERAL DESCRIPTION
The PIC16C62X devices are 18 and 20-Pin ROM/
EPROM-based members of the versatile PICmicro®
family of low-cost, high-performance, CMOS,
fully-static, 8-bit microcontrollers.
All PICmicro microcontrollers employ an advanced
RISC architecture. The PIC16C62X devices have
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a sin-
gle-cycle, except for program branches (which require
two cycles). A total of 35 instructions (reduced instruc-
tion set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.
PIC16C62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C620A, PIC16C621A and PIC16CR620A
have 96 bytes of RAM. The PIC16C622(A) has 128
by tes of R AM. Each de vice has 13 I/O pins an d an 8-b it
timer/counter with an 8-bit programmable prescaler. In
addition, the PIC16C62X adds two analog compara-
tors with a programmable on-chip voltage reference
module. The comparator module is ideally suited for
applic atio ns re qui ring a low-cost ana lo g interf ac e (e .g.,
battery chargers, threshold detectors, white goods
controllers, etc).
PIC16C62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power con-
sumption. There are f our oscillator op tions, of which the
single pin RC oscillator provides a low-cost solution,
the LP osci llator minim izes pow er consumpti on, XT is a
standard crystal, an d the HS is for H igh Speed crystals .
The SLEEP (power-down) mode offers power savings.
The user can wake up the chip from SLEEP through
several external and internal interrupts and reset.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16C62X
mid-range m ic r o c o n tr o l l er fa m ilies.
A simplif ied b lock di agr am of the PIC16C 62X is show n
in Figure 3-1.
The PIC16C62X series fits perfectly in applications
ranging from battery chargers to low-power remote
sensors . The EPROM technology makes customization
of application programs (detection levels, pulse gener-
ation, timers, etc.) extremely fast and convenient. The
small footprint packages make this microcontroller
series perfect for al l app licati ons wi th spa ce lim itatio ns .
Low-cost, low-power, high-performance, ease of use
and I/O flexibility ma ke the PIC16C62X very versatile.
1.1 Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for the PIC16C5X can be easily ported to
PIC16C62X family of devices (Appendix B). The
PIC16C62X family fills the niche for users wanting to
migrate up from the PIC16C5X family and not needing
various peripheral features of other members of the
PIC16XX mid-range microcontroller family.
1.2 Development Support
The PIC16C62X family is suppor ted by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. Third Party “C” compilers
are also available.
PIC16C62X
DS30235H-page 6 1999 Mic rochip Technology Inc.
TABLE 1-1: PIC16C62X FAMILY OF DEVICES
PIC16C620 PIC16C620A(1) PIC16CR620A(2) PIC16C621 PIC16C621A(1) PIC16C622 PIC16C622A(1)
Clock Maximu m Frequency
of Operation (MHz) 20 20 20 20 20 20 20
Memory
EPROM Program
Memory
(x14 w ords)
512 512 512 1K 1K 2K 2K
Data Memory (bytes) 80 96 96 80 96 128 128
Peripherals
Timer Module(s) TMR0 TMR0 TMRO TMR0 TMR0 TMR0 TMR0
Comparators(s) 2 2 2 2 2 2 2
Internal Reference
Voltage Yes Yes Yes Yes Yes Yes Yes
Features
Interrupt Sources 4 4 4 4 4 4 4
I/O Pins 13 13 13 13 13 13 13
Voltage Range (Volts) 2.5-6.0 2.5-5.5 2.0-5.5 2.5-6.0 2.5-5.5 2.5-6.0 2.5-5.5
Brown-out Reset Yes Yes Yes Yes Yes Yes Yes
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note 2: For ROM par ts, operation from 2.0V - 2.5V will require the PIC16LCR62X parts.
1999 Microchip Technology Inc. DS30235H-page 7
PIC16C62X
2.0 PIC16C62X DEVICE VARIETIES
A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C62X Product
Identification System section at the end of this data
sheet. When placing orders, pleas e use this pag e of the
data sheet to specify the correct part number.
2.1 UV Erasa ble Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip’s PICSTART and PRO MATE
programmers both support programming of the
PIC16C62X .
2.2 One-Ti me- Programm able (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
Note: Microchip does not recommend code pro-
tecting windowed devices.
2.3 Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
av ailab le for users who chose not to program a medium
to high quantity of u nits and w hos e c od e p atte rns ha ve
stabilized. The devices are identical to the OTP
devices, but with all EPROM locations and configura-
tion options already programmed by the factory. Cer-
tain code and prototype verification procedures apply
bef ore p roduction shipme nts ar e av ail able . Pleas e con-
tact your Microchip Technology sales office for more
details.
2.4 Serialized
Quick-Turnaround-Production
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
PIC16C62X
DS30235H-page 8 1999 Mic rochip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 9
PIC16C62X
3.0 ARCHITECTURAL OVERVIEW
The hig h perfo rmance of the PIC16C62X f ami ly can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory. Separatin g prog r am and data m emory further
allows instructions to be sized diff erently than 8-bit wide
data word. Instruction opcodes are 14-bits wide making
it possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline over-
laps fetch and execution of instructions. Consequently,
all ins tructions (3 5) e x ecute i n a single-c ycle (2 00 ns @
20 MHz) except for program branches.
The PIC16C620(A) and PIC16CR620A address 512 x
14 on-chip program memory. The PIC16C621(A)
addresses 1K x 14 program memory. The
PIC16C622(A) addresses 2K x 14 program memory.
All pr ogram me mory is internal.
The PIC16C62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C62X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘speci al op tim al s ituations’ m ake pr og r am mi ng w ith th e
PIC16C62X simple yet efficient. In addition, the
learning curve is reduced si gnifican tly.
The PIC16C62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
function s betwe en dat a i n the wo rking regi ste r a nd any
register fil e .
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immedi ate con stant. In sing le op eran d instructi ons , th e
operand is either the W register or a file register.
The W register is an 8-bit working register use d for ALU
operations. It is not an addressable registe r.
Depending on the instruction executed, the ALU may
aff ect the values of th e Carry (C), Di git C arry (DC), an d
Zero ( Z) bits in th e STATUS regis ter . The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
PIC16C62X
DS30235H-page 10 1999 Microchip Technology Inc.
FIGURE 3-1: BLOCK DIAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level S tack
(13-bit) RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
Voltage
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
Devi ce Program Memory Data Memory
(RAM)
PIC16C620
PIC16C620A
PIC16CR620A
PIC16C621
PIC16C621A
PIC16C622
PIC16C622A
512 x 14
512 x 14
512 x 14
1K x 14
1K x 14
2K x 14
2K x 14
80 x 8
96 x 8
96 x 8
80 x 8
96 x 8
128 x 8
128 x 8
8
3
TMR0
I/O Ports
PORTB
Comparator
RA3/AN3
RA2/AN2/VREF
RA1/AN1
RA0/AN0
Reference
RA4/T0CKI
+
-
+
-
1999 Microchip Technology Inc. DS30235H-page 11
PIC16C62X
TABLE 3-1: PIC16C62X PINOUT DESCRIPTION
Name DIP/
SOIC
Pin #
SSOP
Pin # I/O/P
Type Buffer
Type Description
OSC1/CLKIN 16 18 I ST/CMOS Oscillator cr ystal input/external clock source input.
OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode , OSC2 pin outputs
CLKOUT, which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
MCLR/VPP 4 4 I/P ST Master clear (reset) input/programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 17 19 I/O ST Analog comparator input
RA1/AN1 18 20 I/O ST Analog comparator input
RA2/AN2/VREF 1 1 I/O ST Analog comparator input or VREF output
RA3/AN3 2 2 I/O ST Analog comparator input /output
RA4/T0CKI 3 3 I/O ST Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is open
drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT 6 7 I/O TTL/ST(1) RB0/INT can also be selected as an external
interrupt pin.
RB1 7 8 I/O TTL
RB2 8 9 I/O TTL
RB3 9 10 I/O TTL
RB4 10 11 I/O TTL Interrupt on change pin.
RB5 11 12 I/O TTL Interrupt on change pin.
RB6 12 13 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 13 14 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
VSS 5 5,6 P — Ground reference for logic and I/O pins.
VDD 14 15,16 P — Positive supply f or logic and I/O pins.
Legend: O = output I/O = input/output P = power
— = Not used I = Input ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
PIC16C62X
DS30235H-page 12 1999 Microchip Technology Inc.
3.1 Clocking Scheme/Instruction Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then tw o cycles are required t o complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the e x ecu tion cy cle, t he f etche d instructio n is latche d
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memo ry is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
1999 Microchip Technology Inc. DS30235H-page 13
PIC16C62X
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16 C62X has a 13-bit prog ram coun ter capabl e
of ad dressing an 8 K x 14 progr am memory space . Only
the first 512 x 14 (0000h - 01FFh) for the
PIC16C620(A) and PIC16CR620, 1K x 14 (0000h -
03FFh) for the PIC16C621(A) and 2K x 14 (0000h -
07FFh) for the PIC16C622(A) are physically imple-
mented. Accessing a location above these boundaries
will ca use a wrap-ar ound within the firs t 512 x 14 space
(PIC16C(R)620(A)) or 1K x 14 space (PIC16C621(A))
or 2K x 14 space (PIC16C622(A)). The reset vector is
at 0000h and the interrupt vector is at 0004h
(Figure 4-1, Figure 4-2, Figure 4-3).
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK F OR THE
PIC16C620/PIC16C620A/
PIC16CR620A
PC<12:0>
13
000h
0004
0005
01FFh
0200h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-Chip Progr am
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C621/PIC16C621A
FIGURE 4-3: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C622/PIC16C622A
PC<12:0>
13
000h
0004
0005
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-Chip Progr am
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
PC<12:0>
13
000h
0004
0005
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-Chip Prog r am
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
PIC16C62X
DS30235H-page 14 1999 Microchip Technology Inc.
4.2 Data Memory Organization
The data memory (Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7) is partitioned into two banks, which contain the
General Purpose Registers and the Special Function Reg-
isters . Bank 0 is selec ted when the RP0 bi t is cleared. Bank
1 is selected when the RP0 bit (STATUS <5>) is set. The
Special Function Registers are located in the first 32 loca-
tions of each bank. Register locations 20-7Fh (Bank0) on
the PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and
A0-BFh (Bank1) on the PIC16C622 and PIC16C622A are
General Purpose Registers implemented as static RAM.
Some Special Purpose Registers are mapped in Bank 1.
Address es F0h-FF h of bank1 are impl emente d as comm on
ram and mapped back to addresses 70h-7Fh in bank0 on
the PIC16C620A/621A/622A/CR620A.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is organized as 80 x 8 in the
PIC16C620/621, 96 x 8 in the PIC16C620A/621A/
CR620A and 128 x 8 in the PIC16C622(A). Each is
accessed either directly or indirectly through the File
Select Register FSR (Section 4.4).
1999 Microchip Technology Inc. DS30235H-page 15
PIC16C62X
FIGURE 4-4: DATA MEMORY MAP FOR
THE PIC16C62 0/6 21
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
6Fh
70h
Unimplemented data memory locations, read as ’0’.
Note 1: Not a physical register.
File
Address
FIGURE 4-5: DATA MEMORY MAP FOR
THE PIC1 6C6 22
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
BFh
C0h
Unimplemented data memory locations, read as ’0’.
Note 1: Not a physical register.
File
Address
General
Purpose
Register
PIC16C62X
DS30235H-page 16 1999 Microchip Technology Inc.
FIGURE 4-6: DATA MEMORY MAP FOR THE
PIC16C620A/CR620A/621A
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
6Fh
70h
Unimplemented data memory locations, read as ’0’.
Note 1: Not a physical register.
File
Address
Accesses
70h-7Fh
F0h
General
Purpose
Register
FIGURE 4-7: DATA MEMORY MAP FOR
THE PIC16C6 22A
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
BFh
C0h
Unimplemented data memory locations, read as ’0’.
Note 1: Not a physical register.
File
Address
General
Purpose
Register
Accesses
70h-7Fh
F0h
6Fh
70h General
Purpose
Register
1999 Microchip Technology Inc. DS30235H-page 17
PIC16C62X
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). The Special Function
Registers associated with the “core” functions are
described in this section. Those rela ted to the operation
of the peripheral features are described in the section
of that peripheral feature.
TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C62X
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
Value on all
other
resets(1)
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register) xxxx xxxx xxxx xxxx
01h TMR0 Time r0 Mod ule’s Register xxxx xxxx uuuu uuuu
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC
0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA ——— RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h-09h Unimplemented — —
0Ah PCLATH ——— Write buffer f o r upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —CMIF——————-0-- ---- -0-- ----
0Dh-1Eh Unimplemented — —
1Fh CMCON C2OUT C1OUT —— CIS CM2 CM1 CM0 00-- 0000 00-- 0000
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register) xxxx xxxx xxxx xxxx
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC
0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA ——— TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h-89h Unimplemented — —
8Ah PCLATH ——— Write buffer f o r upper 5 bits of program counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 —CMIE——————-0-- ---- -0-- ----
8Dh Unimplemented — —
8Eh PCON ——————PORBOR ---- --0x ---- --uq
8Fh-9Eh Unimplemented — —
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented loc ations read as ‘0’, u = unchanged, x = unknown,
q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during
normal operation.
Note 2: IRP & RP1 bits are reserved; always maintain these bits clear.
PIC16C62X
DS30235H-page 18 1999 Microchip Technology Inc.
4.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 4-1, contains
the arithmeti c status of th e ALU , the RESET statu s and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disab led . The se bi ts ar e set o r clea red a ccordi ng to the
device logi c. Fur t her more, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clea r t he up p er- t h ree
bits a nd se t the Z bit. This lea v es the status regi ster a s
000uu1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary”.
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16C62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits
is NOT recommended, since this may
affect upward compatibility with future
products.
Note 2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
- n = Value at POR reset
- x = Unknown at POR reset
bit0
bit 7: IRP: Register Bank Select bi t (use d for indirect addressi ng)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved on the PIC16C62X ; always maintain this bit clear.
bit 6-5: RP<1:0>: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X ; always maintain this bit clear.
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zer o bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF in structions)(f or borrow the polarity is re ver sed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: F or b orro w the polari ty is reversed. A subtractio n is execut ed by adding the tw o’s comp lem en t of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit
of the source register.
1999 Microchip Technology Inc. DS30235H-page 19
PIC16C62X
4.2.2.2 OPTION REGISTER
The OPTION register is a readable and writable
register , which contai ns various control bits to configu re
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
REGISTER 4-2: OPTION REGIST ER (ADDRESS 81H)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
- n = Value at POR reset
- x = Unknown at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Sour ce Select bit
1 = Transi tion on RA4/T0CKI pin
0 = Internal instruction cycle clo ck (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-t o-low transitio n on RA4/T0CKI pi n
0 = Increment on low-to-high transitio n on RA4/T0CKI pi n
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C62X
DS30235H-page 20 1999 Microchip Technology Inc.
4.2.2.3 INTCON REGISTER
The INTCON register is a readable and writable
register, which co ntains the various e nable and flag bit s
for all i nte rrupt s ourc es except the co mparator m od ule.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.
Note: Interrupt fl ag bits get set wh en an i nterrupt
conditi on oc curs , re gardles s o f the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
- x = Unknown at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
1999 Microchip Technology Inc. DS30235H-page 21
PIC16C62X
4.2.2.4 PIE 1 REGIS TER
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)
4.2.2.5 PIR1 REGIS TER
This regi ster contains the indivi dual flag bit for the
comparator interrupt.
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
—CMIE— — — — — — R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
- n = Value at POR reset
- x = Unknown at POR reset
bit7 bit0
bit 7: Unimplemented: Read as ’0’
bit 6: CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
bit 5-0: Unimplemented: Read as ’0’
Note: Interrupt flag bits get set when an interrupt
conditi on oc curs, rega rdle ss of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bi ts are clear prior to enab ling
an interrupt.
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
—CMIF— — — — — — R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
- n = Value at POR reset
- x = Unknown at POR reset
bit7 bit0
bit 7: Unimplemented: Read as’0’
bit 6: CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5-0: Unimplemented: Read as ’0’
PIC16C62X
DS30235H-page 22 1999 Microchip Technology Inc.
4.2.2.6 PCON REGISTER
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR reset,
WDT reset or a Brown-out Reset.
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR status bit is a "don’t
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming BODEN bit in the
Configuration word).
REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
————— —PORBOR R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
- n = Value at POR reset
- x = Unknown at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as ’0’
bit 1: POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1 = No Brown-out Re set occurred
0 = A Brown-out R eset occurred (must be set in s oftwa re after a Brown- out Res et occurs)
1999 Microchip Technology Inc. DS30235H-page 23
PIC16C62X
4.3 PCL and PCLATH
The program counter (PC) is 13 -bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-8 shows the two
situations for the loading of the PC. The upper e xample in
the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PC H).
FIGURE 4-8: LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1 COMPUTED GOTO
A compu ted GOT O is accomplished b y adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should b e exercised i f t he table location c r os se s a PC L
memory boundary (each 256 byte block). Refer to the
application note,
“Implementing a Table Read"
(AN556).
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO,CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
4.3.2 STACK
The PIC16C62X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data space
and the st ack pointer is no t readable or w ritable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POP ed in the ev ent of a RETURN, RETLW or a RET-
FIE instruc tion execut ion. PCLATH is no t affe cted by
a PUSH or POP operation.
The stack operates as a circular buffer. This means
that after the stack has been PUSHed eight times, the
ninth push overwrites the value that was stored from
the first push. The tenth push overwrites the second
push (and so on) .
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
Note 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
PIC16C62X
DS30235H-page 24 1999 Microchip Technology Inc.
4.4 Indirect Addressing, INDF and FSR
Registers
The INDF re gister is not a ph ysical register . Add ressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the File Select Register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a
no-oper ation (alth ough status bits ma y be af fec ted). An
eff ecti ve 9-bit addr ess is obta ined b y con catenatin g the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-9. However, IRP is not used in the
PIC16C62X .
A simple prog ra m to clear RAM locati on 20h-7Fh usin g
indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
N
EXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,7 ;all done?
goto NEXT ;no clear next
;yes continue
CONTINUE:
FIGURE 4-9: DIRECT/INDIRECT ADDRESSING PIC16C62X
For memory map detail see (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7).
Note1: The RP1 and IRP bits are reserved; always maintain these bits clear.
Data
Memory
Indirect AddressingDirect Addressing
bank select location select
RP1 RP0(1) 60
from opcode IRP(1) FSR register
70
bank select location select
00 01 10 11 180h
1FFh
00h
7Fh Bank 0 Bank 1 Bank 2 Bank 3
not used
1999 Microchip Technology Inc. DS30235H-page 25
PIC16C62X
5.0 I/O PORTS
The PI C16C 62X have two por ts, PORTA and PORTB.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1 PORTA and TRISA Registers
PORT A is a 5-bit wide latch. RA4 is a Schmitt Trigger input
and an open drain output. P ort RA4 is multiplex ed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input lev els and full CMOS output drivers. All pins
have data directi on bits (TRIS re gisters), which can con-
figure these pins as input or output.
A ’1’ in t he TRISA r egister put s the corr esponding ou tput
driver in a hi- impedance mode. A ’0’ in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the POR TA register reads the status of the pins,
whereas writing to it will write to the por t latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
va lue is modified and written to the port data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as ’0’s.
FIGURE 5-1: BLOCK DIAGRAM OF
RA1:RA0 PINS
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog VSS
VDD
I/O
QD
Q
CK
Input Mode
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
VDD
Pin
VSS
TRISA cont rols the directio n of the RA pins , e v en when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
v ery high impe dance outpu t and m us t be b uffered prior
to any external load. The user must configure
TRISA<2> bit as an input and use high impedance
loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared t o enable outputs to us e this func tion.
EXAMPLE 5-1: INITIALIZING PORTA
FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN
Note: On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comp arato r inputs are f orc ed to groun d
to re duce excess current consumption.
CLRF PORTA ;Initialize PORTA by setting
;output data latches
MOVLW 0X07 ;Turn comparators off and
MOVWF CMCON ;enable pins for I/O
;functions
BSF STATUS, RP0 ;Select Bank1
MOVLW 0x1F ;Value used to initialize
;data direction
MOVWF TRISA ;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as ’0’.
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog VSS
VDD
RA2
QD
Q
CK
Input Mode
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
VROE
VREF
VDD
VSS
Pin
PIC16C62X
DS30235H-page 26 1999 Microchip Technology Inc.
FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN
FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog VSS
VDD
RA3 Pin
QD
Q
CK
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
Input Mode
Comparator Output
Comparator Mode = 110
VDD
VSS
Data
Bus QD
Q
CK
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
RA4 Pin
QD
Q
CK
DQ
EN
TMR0 Clock Input
Schmitt Trigger
Input Buffer
Comparator Output
Comparator Mode = 110
VSS
1999 Microchip Technology Inc. DS30235H-page 27
PIC16C62X
TABLE 5-1: PORTA FUNCTIONS
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit # Buffer Typ e Function
RA0/AN0 bit0 ST Input/output or comparator input
RA1/AN1 bit1 ST Input/output or comparator input
RA2/AN2/VREF bit2 ST Input/output or comparator input or VREF output
RA3/AN3 bit3 ST Input/output or comparator input/output
RA4/T0CKI bit4 ST Input/output or external cloc k input f or TMR0 or comparator output.
Output is open drain type.
Legend: ST = Schmit t Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
All Other
Resets
05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
1Fh CMCON C2OUT C1OUT —— CIS CM2 CM1 CM0 00-- 0000 00-- 0000
9Fh VRCON VREN VROE VRR —VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note: Shaded bits are not used by PORTA.
PIC16C62X
DS30235H-page 28 1999 Microchip Technology Inc.
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A ’1’ in
the TRISB register puts the correspondi ng output driv er
in a high impedance mode. A ’0’ in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
wherea s writin g t o i t wil l w rite to the port latch. Al l writ e
oper ations are rea d-modify-write oper ations. So a w rite
to a port implies that the port pins are first read, then
this value is mo dif ied and w ritten to the po rt data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical ). A single control bit can t urn on al l the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when th e port pin is configur ed as an o utput.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (e.g., any RB<7:4> pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are OR’ed togeth er to ge ner ate th e RBIF interrupt (fla g
latched in INTCON<0>).
FIGURE 5-5: BLOCK DIAGRAM OF
RB<7:4> PINS
Data Latch
From other
RBPU(1) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR PORT B
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB<7:4> pins
weak
pull-up
RD PORTB
Latch
TTL
Input
Buffer
pin
Note 1: TRISB = 1 enables weak pull-up if RBPU = ’0’
(OPTION<7>).
ST
Buffer
RB<7:6> in serial programming mode
Q
Q
VCC
VSS
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552, “Implement-
ing Wake-Up on Key Strokes.)
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the in terrup t on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6: BLOCK DIAGRAM OF
RB<3:0> PINS
Note: If a change on the I/O pin should occur
when th e re ad ope r ati on i s bei ng executed
(start of the Q2 cycl e), t hen the RBI F int er-
rupt flag may not get set.
Data Latch
RBPU(1) P
VDD
QD
CK
D
CK
QD
EN
Data Bus
WR PORT B
WR TRISB
RD TRISB
RD PORTB
weak
pull-up
RD PORTB
RB0/INT
I/O
pin
TTL
Input
Buffer
Note 1: TRISB = 1 enables weak pull-up if RBPU = ’0’
(OPTION<7>).
ST
Buffer
Q
Q
Q
VCC
VSS
1999 Microchip Technology Inc. DS30235H-page 29
PIC16C62X
TABLE 5-3: PORTB FUNCTIONS
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit # Buffer Type Function
RB0/INT bit0 TTL/ST(1) Input/output or external interrupt input. Internal software programmable
weak pul l-u p.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/outpu t pin (with in terrupt on ch ange). Internal softw are prog rammab le
weak pul l-u p.
RB5 bit5 TTL Input/outpu t pin (with in terrupt on ch ange). Internal softw are prog rammab le
weak pul l-u p.
RB6 bit6 TTL/ST(2) Input/outpu t pin (with interrupt on change). Internal so ftware prog rammab le
weak pull-up. Serial programming clock pin.
RB7 bit7 TTL/ST(2) Input/outpu t pin (with interrupt on change). Internal so ftware prog rammab le
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Address Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
All Other
Resets
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Note: Shaded bits are not used by PORTB.
u = unchanged
x = unknown
PIC16C62X
DS30235H-page 30 1999 Microchip Technology Inc.
5.3 I/O Programming Considerations
5.3.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU , execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input si gnal present on th e pi n its el f would be read in to
the CPU and re-written to the data latch of this
particular pin, ov erwrit ing the pre viou s content. As lon g
as the pin stays in the input mode, no problem occurs.
However, if bit0 is switched into output mode later on,
the content of the data latch may now be unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read modify write instructions
(ex. BCF, BSF, etc.) on a por t, the v alue of the por t pins
is read, the desire d oper ation is done to th is v alu e, an d
this value is then written to the port latch.
Example 5-2 shows the effect of two sequential
read-mod ify-write ins tructions (ex., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a Low or High should not be
dri ven from exter na l devices at the same time i n or der
to change the le vel on this pin (“wired-or”, “wired-an d”).
The resulting high output currents may damage
the chip.
EXAMPLE 5-2: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.3.2 SUCCESS IVE OPERA T IO NS ON I/ O PORTS
The ac tual write to an I/O port happe ns at th e end o f an
instruct ion cycle, whereas f or readi ng, the data must be
valid at the beginning of the instruction cycle
(Figure 5-7). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into t he CPU is e x ecuted. Othe rwise ,
the pre v ious s tate of th at pin m a y be re ad into t he CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
;
;Initial PORT settings: PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;
;PORTB<7:6> have external pull-up and are not
connected to other circuitry
;
; PORT latch PORT pins
; ---------- ----------
BCF PORTB, 7 ; 01pp pppp 11pp pppp
BCF PORTB, 6 ; 10pp pppp 11pp pppp
BSF STATUS,RP0 ;
BCF TRISB, 7 ; 10pp pppp 11pp pppp
BCF TRISB, 6 ; 10pp pppp 10pp pppp
;
; Note that the user may have expected the pin
; values to be 00pp pppp. The 2nd BCF caused
; RB7 to be latched as the pin value (High).
FIGURE 5-7: SUCCESSIVE I/O OPERATION
Note:
This exampl e shows writ e to PORTB
followed by a read from PORTB.
Note that:
data setu p ti m e = (0.25 T CY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1
cycle to output valid.
Therefore, at higher clock frequen-
cies, a write followed by a read may
be problematic.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q2
Q3 Q4 Q1 Q2 Q3 Q4
R B < 7:0 >
Port pin
sam pled here
PC PC + 1 PC + 2 PC + 3
NOP
NOP
MO VF POR TB, W
Read PORTB
M OVW F POR TB
Write to
PORTB
PC
In structio n
fetched
T
PD
Execute
MOVWF
PORTB
Execute
MOVF
POR TB, W
Execute
NOP
RB<7:0>
PC PC+1 PC+2 PC+3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
NOP
NOP
MOVF, PORTB, W
Read PORTB
MOVWF, PORTB
Write to
PORTB
Port pin
sam pled he re
TPD
Execute
MOVWF
PORTB
Execute
MOVF
PORTB, W
Execute
NOP
PC
Instruction
fetched
1999 Microchip Technology Inc. DS30235H-page 31
PIC16C62X
6.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit soft ware p rogrammable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In tim er mode , the TM R0 will increme nt
ever y instruction cycle (without prescaler). If Timer0 is
wr itten, t he incr ement is inhibit ed for the foll owi ng two
cycles (Figure 6-2 and Figure 6-3). The user can work
around this by writing an adjusted value to TMR0.
Counter mode is selected by setting the T0CS bit. In
this mode, Timer0 will increment either on ever y r ising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
bit (OPTION<4>). Clearing the T0SE bit selects the
rising edge . Restrictio ns on the e xternal cloc k input ar e
dis c ussed in detail in Section 6.2.
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 6.3 details the operation of the
prescaler.
6.1 TIMER0 Interrupt
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before
re-enabling this interrupt. The Timer0 interrupt cannot
wa ke the proces sor from SLEEP, since the timer is shut
off during SLEEP. See Figure 6-4 for Timer0 interrupt
timing.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
FIGURE 6-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
Note 2: The prescaler is shared with Watchdog Timer (Figure 6-6).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks TMR0
PSout
(2 TCY delay)
PSout
Data Bus
8
Set Flag bit T0IF
on Overflow
PSA
PS<2:0>
PC-1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
Instruction
Fetch
TMR0
PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
T0 T0+1 T0+2 NT0 NT0+1 NT0+2 T0
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PIC16C62X
DS30235H-page 32 1999 Microchip Technology Inc.
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
FIGURE 6-4: TIMER0 INTERRUPT TIMING
PC-1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
Instruction
Fetch
TMR0
PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
T0 NT0+1
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1
T0+1 NT0
Instruction
Execute
Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
11
OSC1
CLKOUT(3)
TMR0 timer
T0IF bit
(INTCON<2>)
FEh
GIE bit
(INTCON<7>)
INSTRUCT ION FLOW
PC
Instruction
fetched
PC PC +1 PC +1 0004h 0005h
Instruction
executed
Inst (PC)
Inst (PC-1)
Inst (PC+1)
Inst (PC)
Inst (0004h) Inst (0005h)
Inst (0004h)Dummy cycle Dummy cycle
FFh 00h 01h 02h
Note 1: T0IF interrupt flag is sampled here (every Q1).
Note 2: Interrupt latency = 3TCY, where TCY = instruction cycle time.
Note 3: CLKOUT is available only in RC oscillator mode.
Interrupt Latency Time(2)
1999 Microchip Technology Inc. DS30235H-page 33
PIC16C62X
6.2 Using Timer0 with External Clock
When an e xternal clock inp ut is used f or Timer0 , it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1 EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the exter nal clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small R C del ay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
accoun t. Th erefore, it is neces sa ry for T0CKI to have a
period of at lea st 4TOSC (and a small RC dela y of 40 ns)
divide d by the prescaler v alue. The only require ment on
T0CKI high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
par am ete rs 40, 4 1 and 42 i n the electrical s pec if ica tio n
of the desired device.
6.2.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 6-5 shows the delay from
the external clock edge to the timer incrementing.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Exter nal Clock Input or
Prescaler output (2)
Exter nal Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
Note 1: Delay from clock input change to Timer0 increm ent is 3Tosc to 7Tosc. (Duration of Q = To sc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
Note 2: Exter nal clock if no prescaler selected, Prescaler output otherwise.
Note 3: The arrows indicate the points in time where sampling occurs.
(3) (1)
PIC16C62X
DS30235H-page 34 1999 Microchip Technology Inc.
6.3 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 6-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x....etc.) will clear the prescaler.
When assi gned to WDT, a CLRWDT instruction will clear
the prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
T0CKI
T0SE
pin
M
U
X
CLKOUT (= FOSC/4)
SYNC
2
Cycles TMR0 reg
8-bit Prescaler
8-to-1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS<2:0>
8
Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflo w
8
PSA
T0CS
1999 Microchip Technology Inc. DS30235H-page 35
PIC16C62X
6.3.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
RESET, the following instruction sequence
(Example 6-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
EXAMPLE 6-1: CHANGING PRE SCALER
(TIMER0→WDT)
1.BCF STATUS, RP0 ;Skip if already in
; Bank 0
2.CLRWDT ;Clear WDT
3.CLRF TMR0 ;Clear TMR0 & Prescaler
4.BSF STATUS, RP0 ;Bank 1
5.MOVLW '00101111’b; ;These 3 lines (5, 6, 7)
6.MOVWF OPTION ; are required only if
; desired PS<2:0> are
7.CLRWDT ; 000 or 001
8.MOVLW '00101xxx’b ;Set Postscaler to
9.MOVWF OPTION ; desired WDT rate
10.BCF STATUS, RP0 ;Return to Bank 0
To change prescaler from the WDT to the TMR0
module , u se th e se quenc e sh ow n in Example 6-2. This
precaution must be taken even if the WDT is disabl ed.
EXAMPLE 6-2: CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT ;Clear WDT and
;prescaler
BSF STATUS, RP0
MOVLW b'xxxx0xxx' ;Select TMR0, new
;prescale value and
;clock source
MOVWF OPTION_REG
BCF STATUS, RP0
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
All Other
Resets
01h TMR0 Timer0 module register xxxx xxxx uuuu uuuu
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA — — —TRISA4TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: — = Unimplemented locations, read as ‘0’.
Note: Shaded bits are not used by TMR0 module.
u = unchanged
x = unknown
PIC16C62X
DS30235H-page 36 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 37
PIC16C62X
7.0 COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The
On-Chip Voltage Reference (Section 8.0) can also be
an input to the comparators.
The CMCON register, shown in Register 7-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 7-1.
REGISTER 7-1: CMCON REGISTER (ADDRESS 1Fh)
R-0 R-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
C2OUT C1OUT —— CIS CM2 CM1 CM0 R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
- n = Value at POR reset
- x = Unknown at POR reset
bit7 bit0
bit 7: C2OUT: Comparator 2 output
1 = C2 VIN+ > C2 VIN–
0 = C2 VIN+ < C2 VIN–
bit 6: C1OUT: Comparator 1 output
1 = C1 VIN+ > C1 VIN–
0 = C1 VIN+ < C1 VIN–
bit 5-4: Unimplemented: Read as '0'
bit 3: CIS: Comparator Input Switch
When CM<2:0>: = 001:
1 = C1 VIN– connects to RA3
0 = C1 VIN– connects to RA0
When CM<2:0> = 010:
1 = C1 VIN– connects to RA3
C2 VIN– connects to RA2
0 = C1 VIN– connects to RA0
C2 VIN– connects to RA1
bit 2-0: CM<2:0>: Comparator mode.
PIC16C62X
DS30235H-page 38 1999 Microchip Technology Inc.
7.1 Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 7-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the comparator
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 12 -2.
Note: Comparator interrupts should be disabled
during a comparator mode change other-
wise a f a ls e inte rrupt may occur.
FIGURE 7-1: COMPARATOR I/O OPERATING MODES
-
+C1
VIN-
VIN+Off
(Read as ’0’)
RA0/AN0
RA3/AN3
A
A
CM<2:0> = 000
-
+C2
VIN-
VIN+Off
(Read as ’0’)
RA1/AN1
RA2/AN2
A
A
-
+C1
VIN-
VIN+Off
(Read as ’0’)
RA0/AN0
RA3/AN3
D
D
CM<2:0> = 111
-
+C2
VIN-
VIN+Off
(Read as ’0’)
RA1/AN1
RA2/AN2
D
D
-
+C1
VIN-
VIN+C1OUT
RA0/AN0
RA3/AN3
A
A
-
+C2
VIN-
VIN+C2OUT
RA1/AN1
RA2/AN2
A
A
CM<2:0> = 100
-
+C1
VIN-
VIN+C1OUT
RA0/AN0
RA3/AN3
A
A
-
+C2
VIN-
VIN+C2OUT
RA1/AN1
RA2/AN2
A
A
From VREF Module
-
+C1
VIN-
VIN+C1OUT
RA0/AN0
RA3/AN3
A
D
-
+C2
VIN-
VIN+C2OUT
RA1/AN1
RA2/AN2
A
A
CM<2:0> = 011 RA4 Open Drain
-
+C1
VIN-
VIN+C1OUT
RA0/AN0
RA3/AN3
A
D
-
+C2
VIN-
VIN+C2OUT
RA1/AN1
RA2/AN2
A
A
CM<2:0> = 110
-
+C1
VIN-
VIN+Off
(Read as ’0’)
RA0/AN0
RA3/AN3
D
D
CM<2:0> = 101
-
+C2
VIN-
VIN+C2OUT
RA1/AN1
RA2/AN2
A
A
-
+C1
VIN-
VIN+C1OUT
RA0/AN0
RA3/AN3
A
A
-
+C2
VIN-
VIN+C2OUT
RA1/AN1
RA2/AN2
A
A
CM<2:0> = 001
CIS=0
CIS=1
Comparators Reset
Two Independent Comparators
Two Common Reference Comparat ors
One Independent Comparator Three Inputs Multiplexed to
Two Common Reference Comparators with Outputs
Four Inputs Multiplexed to
Comparators Off
Two Comparators
Two Comparators
CM<2:0> = 010
CIS=0
CIS=1
CIS=0
CIS=1
A = Analog Input, Port Reads Zeros Always
D = Digital Input
CIS = CMCON<3>, Comparator Input Switch
1999 Microchip Technology Inc. DS30235H-page 39
PIC16C62X
The code example in Example 7-1 depicts the steps
required to confi gure the co mp arator module. R A3 an d
RA4 are confi gured as digita l output. RA0 and R A1 are
configured as the V- inputs and RA2 as the V+ input to
both co mp ar ators.
EXAMPLE 7- 1: INITIALIZING
COMPARATOR MODULE
7.2 Comparator Operation
A sing le com parator is shown i n Figu re 7- 2 alo ng with
the relationship between the analog input levels and
the digit al output. Wh en the anal og input at V IN+ is less
than the analog input VIN–, the output of the
compar ator is a digital lo w le v el. Wh en the anal og input
at VIN+ is great er than the analog input VIN–, the output
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 7-2
represent the uncertainty due to input offsets and
response time.
MOVLW 0x03 ;Init co mpar ator mode
MOVWF CMCON ;CM<2:0> = 011
CLRF PORTA ;In it PO RTA
BSF ST ATUS,RP0 ;Select Bank 1
MOVLW 0x07 ;Initial ize data direction
MOVWF TRISA ;Set RA< 2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> alway s read ‘0’
BCF ST ATUS,RP0 ;Select Bank 0
CALL DELAY 10 ;10µs delay
MOVF CMCON,F ;Read CMCON to end change condition
BCF PI R1,CM IF ;Clear pending interrupts
BSF ST ATUS,RP0 ;Select Bank 1
BSF PI E1,CMIE ;Enable comparato r interrupts
BCF ST ATUS,RP0 ;Select Bank 0
BSF IN TCON,PEIE ;Enable periphera l interru pts
BSF IN TCON,GIE ;Global inte rrupt enable
7.3 Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog sign al th at is pr esent at VIN– is compa red to the
signal at VIN+, and the digital output of the comparator
is ad justed accordingly (Figure 7-2).
FIGURE 7-2: SINGLE COMPARATOR
7.3.1 EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
compar ator module can be configured to hav e the com-
parators operate from the same or different reference
sources. Ho wever , t hres ho ld det ector applic ati ons m ay
require the same reference. The reference signal must
be bet we en V SS an d VDD, and can b e app li ed to eith er
pin of the comparator(s).
7.3.2 INTERNAL REFERENCE SIGNAL
The com pa r a tor mo dule also a llows the se lec ti on of an
internally generated voltage reference for the
comparators. Section 10, Instruction Sets, contains a
detailed description of the Voltage Reference Module
that provides this signal. The internal reference signal
is used when the comparators are in mode
CM<2:0>=010 (Figure 7-1). In this mode, the internal
voltage reference is applied to the VIN+ pin of both
comparators.
–
+
VIN+
VIN–Output
VIN–
VIN+
Output
Output
VIN+
VIN–
PIC16C62X
DS30235H-page 40 1999 Microchip Technology Inc.
7.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
compar ator outp ut has a va lid le v el. If the internal ref er-
ence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise the maximum delay of
the comparators should be used (Table 12-2 ).
7.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
output s ma y also be directly o utput to the RA3 and R A4
I/O pins. When the CM<2:0> = 110, multiplexors in the
output pa th of the RA3 an d RA4 pins wil l switc h and the
output of ea ch pin wi ll b e the uns yn ch ronized ou tpu t of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 7-3 shows the compar ator output b lock diagram.
The TRISA bits will still function as an output
enable/disable for the RA3 and RA4 pins while in this
mode.
Note 1: When reading the POR T register , al l pins
configured as analog inputs will read as
a ‘0’. Pi ns con figu red a s di gital inpu ts w ill
conver t a n an al o g i npu t ac co rdi n g t o the
Schmitt Trigger input specification.
Note 2: Analog levels on any pin that is defined
as a digital input may cause the input
buffer to consume more current than is
specified.
FIGURE 7-3: COMPARATOR OUTPUT BLOCK DIAGRAM
DQ
EN
To RA3 or
RA4 Pin
Bus
Data
RD CMCON
Set
MULTIPLEX
CMIF
Bit
-+
DQ
EN
CL
Port Pins
RD CMCON
NRESET
From
Other
Comparator
1999 Microchip Technology Inc. DS30235H-page 41
PIC16C62X
7.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status o f the output bit s, as r ead from CMCON<7 :6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also p ossible to w rite a '1 ' to this r egister, a simulat ed
interrupt may be initiated.
The CMIE bit (PIE1<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
The user, in the interrupt serv ice routine, can clear the
interrup t in the following manner:
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Readi ng C M CO N will end the mism at ch condition, and
allow flag bit CMIF to be cleared.
7.7 Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
Note: If a change in the CMCON register
(C1OUT or C2O UT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
wake up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher sleep
currents than shown in the power down current
specification will occur. Each comparator that is
oper ational will consume additional current as s hown i n
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = 111, before entering sleep. If
the device wakes-up from sleep, the contents of the
CMCON register are not affected.
7.8 Effects of a RESET
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM<2:0> = 000. This ensures
that all potential inputs are analog inputs. Device cur-
rent is minimized when analog inputs are present at
reset time. The comparators will be powered-down
during the reset interval.
7.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 7-4: ANALOG INPUT MODEL
VA
RS < 10K
AIN CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
PIC16C62X
DS30235H-page 42 1999 Microchip Technology Inc.
TABLE 7-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Legend: x = unknown, u = unchanged, - = unimplemented, read as "0"
Address Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
All Other
Resets
1Fh CMCON C2OUT C1OUT —— CIS CM2 CM1 CM0 00-- 0000 00-- 0000
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —CMIF——————-0-- ---- -0-- ----
8Ch PIE1 —CMIE——————-0-- ---- -0-- ----
85h TRISA ———TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
1999 Microchip Technology Inc. DS30235H-page 43
PIC16C62X
8.0 VOLTAGE REFERENCE
MODULE
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The r esistor l adder is segmented to prov ide tw o range s
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
ref ere nce as sho w n in Regis ter 8-1. The bloc k d iagr a m
is given in Figure 8-1.
8.1 Configuring the Voltage Reference
The Voltage Reference can output 16 distinct voltage
levels for each range. The equations used to calculate
the output of the Voltage Reference are as follows:
if VRR = 1: VREF = (VR<3:0>/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Ta ble 12-1). Example 8-1 sh ows an ex ample of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
REGISTER 8-1: VRCON REGISTER(ADDRESS 9Fh)
FIGURE 8-1: VOLTAGE REFERENCE BLOCK DIAGRAM
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN VROE VRR —VR3 VR2 VR1 VR0 R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
- n = Value at POR reset
- x = Unknown at POR reset
bit7 bit0
bit 7: VREN: VREF Enabl e
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6: VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5: VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4: Unimplemented: Read as ’0’
bit 3-0: VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
when VRR = 1: VREF = (VR<3:0>/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
Note: R is defined in Table 12-2.
VRR
8R
VR3
VR0(From VRCON<3:0>)
16-1 Analog Mux
8R RRRR
VREN
VREF
16 Stages
PIC16C62X
DS30235H-page 44 1999 Microchip Technology Inc.
EXAMPLE 8-1: VOLTAGE REFERENCE
CONFIGURATION
8.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 8-1) keep VREF from approaching VSS or V DD.
The v olta ge ref erenc e is VDD de rived and the refo re, the
VREF output changes with fluctuations in VDD. The
test ed absol ute accu racy of th e volt age referenc e can
be found in Table 12-2.
8.3 Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Ti mer time -ou t, the con tents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the voltage
reference should be disabled.
MOVLW 0x02 ; 4 Inputs Muxed
MOVWF CMCON ; to 2 comps.
BSF STATUS,RP0 ; go to Bank 1
MOVLW 0x0F ; RA3-RA0 are
MOVWF TRISA ; inputs
MOVLW 0xA6 ; enable VREF
MOVWF VRCON ; low range
; set VR<3:0>=6
BCF STATUS,RP0 ; go to Bank 0
CALL DELAY10 ; 10µs delay
8.4 Effects of a Reset
A device reset disables the voltage reference by clear-
ing bit VREN (VRCO N<7>). Th is res et also disconne ct s
the reference from the RA2 pin by clearing bit VROE
(VRCON<6>) and selects the high voltage range by
clearing bit VRR (VRCON<5>). The VREF value select
bits, VRCON<3:0>, are also cleared.
8.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit is set and the VROE bit, VRCON<6>, is
set. Enab ling the v oltage ref erence output onto the RA2
pin with an input signal present will increase current
consumption. Connecting RA2 as a digital output with
VREF enabled will also increase current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
voltage reference output for external connections to
VREF. Figure 8-2 shows an example buffering
technique.
FIGURE 8-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 8-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Note: - = Unimplemented, read as "0"
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value On
POR
Value On
All Other
Resets
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
VREF Output
+
–•
•
VREF
Module
Voltage
Reference
Output
Impedance
R(1) RA2
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
1999 Microchip Technology Inc. DS30235H-page 45
PIC16C62X
9.0 SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real ti me appli-
cations are what s ets a micr ocontroller a part from other
process ors . The PIC1 6C62 X fam ily has a host of s uch
features intended to maximize system reliability, mini-
mize cost through elimination of external components,
provide power saving operating modes and offer code
protection.
These are:
1. OSC selection
2. Reset
Power-on Reset (POR)
Power-up Tim er (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOR)
3. Interrupts
4. Watchdog Timer (WDT)
5. SLEEP
6. Code protection
7. ID Locations
8. In-circuit serial programming
The PIC16C62X devices have a Watchdog Timer,
which is controlled by configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on po w e r-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chi p in rese t until th e crystal osci llator is stab le. Th e
other is th e Power-up Timer (PWRT), which pro vi des a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which provides at least a
72 ms reset. With these three functions on-chip, most
applications need no external reset circuitry.
The SLEEP mode is designed to offer a very low
current po wer-do wn mode . The user can w ake-up from
SLEEP through external reset, Watchdog Timer
wake-up or through an interrupt. Several oscillator
opti ons are al so made available t o allow the p ar t to fit
the application. The RC oscillator option saves system
cost, while the LP cr ystal option saves power. A set of
configuration bits are used to select various options.
PIC16C62X
DS30235H-page 46 1999 Microchip Technology Inc.
9.1 Configuration Bits
The con figur ati on bits c an be prog ra mmed (rea d as ’0’)
or left unprogrammed (read as ’1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is be yond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(200 0h – 3FF Fh ), whic h c an be ac cess ed on ly du r ing
programming.
FIGURE 9-1: CONFIGURATION WORD
CP1 CP0(2) CP1 CP0(2) CP1 CP0(2) —BODEN
(1) CP1 CP0(2) PWRTE(1) WDTE F0SC1 F0SC0 CONFIG Address
REGISTER: 2007h
bit13 bit0
bit 13-8, CP<1:0>: Code protection bit pairs(2)
5-4: Code protecti on for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFh code protected
Code protection for 1K progr a m memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
Code protection for 0.5K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = Program memory code protection off
00 = 0000h-01FFh code protected
bit 7: Unimplemented: Read as ’1’
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1, 3)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brow n-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. We
recommend that whenever Brown-out Reset is enabled, the Power-up Timer is also enabled.
Note 2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
Note 3: Unprogrammed par t s default the Power-up Timer disabled.
1999 Microchip Technology Inc. DS30235H-page 47
PIC16C62X
9.2 Oscillator Configurations
9.2.1 OSCILLATOR TYPES
The PIC 16C62X de vices can be operated in fo ur diff er-
ent oscillator options. The user can program two
configu ration b its (FOSC1 and FOSC 0) to select one of
these four modes:
• LP Low Power Crysta l
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor
9.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 9-2). The PIC16C62X oscillator
design requires the use of a parallel cut cr ystal. Use of
a series cut crystal may give a frequency out of the
crystal man ufac turers speci fications . When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 9-3).
FIGURE 9-2: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
FIGURE 9-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
See Table 9-1 and Table 9-2 for recommended
values of C1 and C2.
Note: A series resistor may be required for
AT strip cu t crystals.
C1
C2
XTAL
OSC2
RS
OSC1
RF SLEEP
To internal logic
PIC16C62X
See Note
Clock from
ext. system PIC16C62X
OSC1
OSC2
Open
TABLE 9-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
TABLE 9-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Ranges Characterized:
Mode Freq OSC1(C1) OSC2(C2)
XT 455 kHz
2.0 MHz
4.0 MHz
22 - 100 pF
15 - 68 pF
15 - 68 pF
22 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
Higher capacitance increases the stability of the oscillator
but also increases the start-up time. These values are for
design guidance only. Since each resonator has its own
characteristics, the user s hould consult the res onator man-
ufacturer for appropriate values of external components.
Mode Freq OSC1(C1) OSC2(C2)
LP 32 kHz
200 kHz 68 - 100 pF
15 - 30 pF 68 - 100 pF
15 - 30 pF
XT 100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
HS 8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
Higher capacitance increases the stability of the oscillator
but also increases the start-up time. These values are for
design guidance only. Rs may be required in HS mode as
well as XT mode to avoid overdriv ing crystals with low drive
level specification. Since each crystal has its own
characteristics, the user should consult the crystal manu-
facturer for appropriate values of external components.
PIC16C62X
DS30235H-page 48 1999 Microchip Technology Inc.
9.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance or one with parallel
resonance.
Figure 9- 4 shows imp lementation of a par allel resona nt
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
FIGURE 9-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Figure 9-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter perfor ms a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 9-5: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
20 pF
+5V
20 pF
10k 4.7k
10k
74AS04
XTAL
10k
74AS04 PIC16C62X
CLKIN
To Other
Devices
330 kΩ
74AS04 74AS04 PIC16C62X
CLKIN
To Other
Devices
XTAL
330 kΩ
74AS04
0.1 µF
9.2.4 RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead fram e c ap ac ita nce be tw e en package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 9-6 shows how the
R/C combination is connected to the PIC16C62X. For
Rext values below 2.2 kΩ, the oscillator operation may
become unstable or stop completely . For very high Rext
v alu es (e.g., 1 MΩ), th e osci llator b ecome s sens itiv e to
noise, humidity and leakage. Thus, we recommend to
keep Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
See Section 13.0 for RC frequency variation from par t
to part due t o normal pr ocess v ariati on. The va riation is
larger for larger R (since leakage current variation will
aff ect RC freque ncy mo re f or large R) and for smalle r C
(since variation of input capacitance will affect RC fre-
quency more).
See Section 13.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values, as well as
frequency variation due to operating temperature for
given R, C and VDD v al ues.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (Figure 3-2 for
waveform).
FIGURE 9-6: RC OSCILLATOR MODE
OSC2/CLKOUT
Cext
Rext
VDD
PIC16C62X
OSC1
FOSC/4
Internal Clock
VDD
1999 Microchip Technology Inc. DS30235H-page 49
PIC16C62X
9.3 Reset
The PIC16C62X differentiates between various kinds
of reset:
a) Power-on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT reset (nor mal operation)
e) WDT wake-up (SLEEP)
f) Brown-out Reset (BOR)
Some registers are not affected in any reset condition
Their statu s is unknown on POR and uncha nged in any
other reset. Most other registers are reset to a “reset
state” on Po wer-on reset, MCLR reset, WDT reset and
MCLR re s et du r i ng S L E EP. Th ey a r e no t a ffec ted by a
WDT wake-up, since this is viewed as the resumption
of normal operation. TO and PD bits are set or cleared
differently in different reset situations as indicated in
Table 9-4. These bits are used in software to determine
the nature of th e res et. S ee Table 9-7 for a fu ll des crip-
tion of reset states of all registers.
A simplifi ed b loc k diag ram of the on-ch ip res et circui t is
shown in Figure 9-7.
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 12-5 for pulse width
specification.
FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/
VDD
OSC1/
WDT
Module
VDD rise
detect
OST/PWRT
On-chip(1)
RC OSC
WDT
Time-out
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple-counter
Reset
Enable OST
Enable PWRT
SLEEP
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
CLKIN
Pin
VPP Pin
10-bit Ripple-counter
Q
PIC16C62X
DS30235H-page 50 1999 Microchip Technology Inc.
9.4 Power-on Reset (POR), P ower-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
9.4.1 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
VDD has reache d a high enough le v el f or proper op er a-
tion. To take advantage of the POR, just tie the MCLR
pin th ro ugh a resi stor to VDD. This will eliminate exter-
nal RC components usual ly needed to cre ate Power-on
Reset. A maximum rise time for VDD is required. See
Electrical Specifications for details.
The POR circuit does not produce an internal reset
when VDD declines.
When the device starts normal operation (exits the
reset co ndi tion), de v ic e op er ati ng p arameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be h eld in re set unt il the o per ating condi tio ns are
met.
For additional information, refer to Application Note
AN607, “Power-up Tr ouble Shoot ing”.
9.4.2 POWER-UP TIMER (PWRT)
The Power-up T imer pr ovides a fixed 72 ms (nomi nal)
time-out on power-up only, from POR or Brown-out
Reset . The P ow er-up Timer ope rates on an internal RC
oscillator. The chip is kept in reset as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
disab le (if s et) or enab le (i f cleared or progr ammed) th e
P ower-up Timer . The P ow er-up Timer shoul d always be
enabled when Brown-out Reset is enabled.
The Power-Up Time delay will vary from chip to chip
and due to VDD, temperature and process variation.
See DC parameters for details.
9.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
9.4.4 BROWN-OUT RESET (BOR)
The PIC16C62X members have on-chip Brown-out
Reset circuitry . A configuration bit, BODEN, can disable
(if clear/programmed) or enable (if set) the Brown-out
Reset circuitry. If VDD falls below 4.0V refer to VBOR
parameter D005 (VBOR) for greater than parameter
(TBOR) in Table 12-5. The brown-out situation will
reset the chip. A reset won’t occur if VDD falls below
4.0V for less than parameter (TBOR).
On any reset (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in Reset until VDD rises above
BVDD. The P o wer-up Tim er will now be inv oked an d will
keep the chip in reset an additional 72 ms.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initi alize d. Once VDD
rises above BVDD, the Power-Up Timer will execute a
72 ms reset. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-8
shows typical Brown-out situations.
FIGURE 9-8: BROWN-OUT SITUATIONS
72 ms
BVDD
VDD
Internal
Reset
BVDD
VDD
Internal
Reset 72 ms
<72 ms
72 ms
BVDD
VDD
Internal
Reset
1999 Microchip Technology Inc. DS30235H-page 51
PIC16C62X
9.4.5 TIME-OUT SEQUENCE
On pow er-up the time-out se que nc e is as follo w s: First
PWR T time-out i s inv oked af ter POR has e xpired. Then
OST is activated. The total time-out will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no time-out at all. Figure 9-9,
Figure 9-10 and Figure 9-11 depict time-out
sequences.
Since the time-outs occu r from the POR pulse , if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-10). This is useful for tes ting purposes or
to synchronize more than one PIC16C62X device
operating in parallel.
Table 9-6 shows the reset conditions for some special
register s, while Table 9-7 shows the reset conditions f or
all the registe r s.
9.4.6 POWER CONTROL (PCON)/
STATUS REGISTER
The power control/status register, PCON (address
8Eh), has two bits.
Bit0 is BOR (Brown-out). BOR is unknown on
power-on-reset. It must then be set by the user and
checked on subsequent resets to see if BOR = 0,
indicating that a brown-out has occurred. The BOR
status bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BODEN bit = 0 in the Configuration word).
Bit1 is POR (Power-on-reset). It is a ‘0’ on
power-on-reset and unaffected otherwise. The user
must write a ‘1’ to this bit following a power-on-reset.
On a subse quent re set, if PO R is ‘0’ , it will i ndi cate th at
a power-on-reset must have occurred (VDD may have
gone too low).
TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
Legend: u = unchanged, x = unknown
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: Other (non-power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during
normal oper atio n.
Oscillator Co nfigu ration Power-up Brown-out Reset Wake-up
from SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC
RC 72 ms — 72 ms —
POR BORTO PD
0X11Power-on-reset
0X0XIllegal, TO is set on POR
0XX0Illegal, PD is set on POR
10XXBrown-out Reset
110uWDT Reset
1100WDT Wake-up
11uuMCLR reset duri ng normal operation
1110MCLR reset during SLEEP
TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR
Reset V alue on all
othe r re set s(1)
83h STATUS TO PD 0001 1xxx 000q quuu
8Eh PCON ——————PORBOR---- --0x ---- --uq
PIC16C62X
DS30235H-page 52 1999 Microchip Technology Inc.
TABLE 9-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS
Condition Program
Counter STATUS
Register PCON
Register
Power-on Re se t 000h 0001 1xxx ---- --0x
MCLR reset duri ng normal operation 000h 000u uuuu ---- --uu
MCLR reset during SLEEP 000h 0001 0uuu ---- --uu
WDT reset 000h 0000 uuuu ---- --uu
WDT Wake-u p PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 000x xuuu ---- --u0
Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector
(0004h) after execution of PC+1.
Register Address Power-on Rese t
•MCLR
Reset during
normal operation
•MCLR
Reset during
SLEEP
• WDT Reset
• Brown-out Reset (1)
• W a ke up from SLEEP
through interrupt
• W a ke up from SLEEP
thr ough WDT t ime-out
W- xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h -- -
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h ---x xxxx ---u uuuu ---u uuuu
PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu
CMCON 1Fh 00-- 0000 00-- 0000 uu-- uuuu
PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh 0000 000x 0000 000u uuuu uqqq(2)
PIR1 0Ch -0-- ---- -0-- ---- -q-- ----(2,5)
OPTION 81h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h ---1 1111 ---1 1111 ---u uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch -0-- ---- -0-- ---- -u-- ----
PCON 8Eh ---- --0x ---- --uq(1,6) ---- --uu
VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu
Legend: u = unchanged, x = unknown, - = unimplement ed bit, reads as ‘0’,q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
Note 2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
Note 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
Note 4: See Table 9-6 for rese t value for specific condition.
Note 5: If wake-up was due to compar ator input changing, then bit 6 = 1. All other interrupts generati ng a wake- up will ca use bit 6 = u.
Note 6: If reset was due to bro w n-out, then bit 0 = 0. All other resets will cause bit 0 = u.
1999 Microchip Technology Inc. DS30235H-page 53
PIC16C62X
FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NO T TIED TO VDD): CASE 1
FIGURE 9-10: TIME-OUT SEQUENCE ON POWER- UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 9-11: TIME-OUT SEQUENCE ON POWER- UP (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PIC16C62X
DS30235H-page 54 1999 Microchip Technology Inc.
FIGURE 9-12: EXTERN AL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 9-13: EXTERN AL BROWN-OUT
PROTEC TION CIRCUIT 1
Note 1: External pow er-on reset circuit is required
only if VDD power-up slope is too slow.
The diode D helps discha rge the capaci-
tor quickly when VDD power s down.
Note 2: < 40 kΩ is recommended to make sure
that voltage drop across R does not vio-
late the device’s electrical specification.
Note 3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capaci-
tor C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
RD
VDD
MCLR
PIC16C62X
VDD
Note 1: This circuit will activate reset when VDD
goes belo w (Vz + 0 .7V) where Vz = Zener
voltage.
Note 2: Internal Brown-out Reset circuitry should
be disabled when using this circuit.
VDD 33k
10k
40k
VDD
MCLR
PIC16C62X
FIGURE 9-14: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
FIGURE 9-15: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
Note 1: This bro wn- out circui t is less e xpen siv e ,
albeit l ess accu r ate . Transistor Q1 tu rns
off when VDD is below a certain level
such that:
Note 2: Internal brown-out reset should be dis-
abled when using this circuit.
Note 3: Resistors should be adjusted for the
characteristics of the transisto r.
VDD x R1
R1 + R2 = 0.7 V
VDD
R2 40k
VDD
MCLR
PIC16C62X
R1
Q1
This brown-out protection circuit employs
Microchip Technology’s MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX families
of supervisors provide push-pull and open
collector outputs with both high and low active
reset pins. There are 7 different trip point
selections to accommodate 5V and 3V systems.
MCLR
PIC16C62X
VDD
Vss
RST
MCP809
VDD
bypass
capacitor VDD
1999 Microchip Technology Inc. DS30235H-page 55
PIC16C62X
9.5 Interrupts
The PIC16C62X has 4 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB<7:4>)
• Comparator interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enable RB0/INT interrupts .
The INT pin in terrupt, the RB port change inte rrupt and
the TM R0 overflow int err upt flag s are co ntai ned in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The co rresponding in terrupt enab le bit is
contain ed in special regist ers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stac k and the PC is loa ded with 0004 h.
Once in the interrupt service routine, the source(s) of
the interrupt can be determ ined by polling the interrupt
flag bit s. The interrupt flag bit(s) must be cleared in so ft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the inte rrupt ev ent occ urs (Figure 9-17).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests.
Note 1: Individual interrupt flag bits are set
regardless of the status of their cor-
responding mask bit or the GIE bit.
Note 2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
FIGURE 9-16: INTE RRUPT LOGIC
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
PEIE
Wake-up
(If in SLEEP mode)
Interrupt
to CPU
CMIE
CMIF
PIC16C62X
DS30235H-page 56 1999 Microchip Technology Inc.
9.5.1 RB0/INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered,
eith er r i sing i f IN TED G bi t ( OPTI ON< 6>) i s s et, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control b it (INTCON< 4>). The INT F bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
inte rr upt vector foll owing wake-u p. See S ecti on 9.8 for
details on SLEEP and Figure 9-19 for timing of
wake -up from SLEEP through RB0/INT interrupt.
9.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Sectio n 6.0.
9.5.3 PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
9.5.4 COMPARATOR INTERRUPT
See Secti on 7.6 fo r complete description of comparat or
interrupts.
Note: If a change on the I/O pin should occur
when th e re ad ope r ati on i s bei ng executed
(start of the Q2 cycl e), t hen the RBI F int er-
rupt flag may not get set.
FIGURE 9-17: INT PIN INTERRUPT TIMING
TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR
Reset V alue on all
othe r re set s(1)
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —CMIF— — — — — — -0-- ---- -0-- ----
8Ch PIE1 —CMIE— — — — — — -0-- ---- -0-- ----
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Interrupt Latency
PC PC+1 PC+1 0004h 0005h
Inst (0004h) Inst (0005h)
Dummy Cycle
Inst (PC) Inst (PC+1)
Inst (PC-1) Inst (0004h)
Dummy Cycle
Inst ( PC)
—
1
4
51
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interr upt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is av ailable only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
2
3
1999 Microchip Technology Inc. DS30235H-page 57
PIC16C62X
9.6 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (e.g. W register and STATUS
registe)r. This will have to be implemented in software.
Example 9-1 stores and restores the STATUS and W
register s. The u ser regi ster, W_TEMP, mus t be de fined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user regi ster, STATUS_TEM P, must be
defined in Bank 0. The Example 9-1:
• Stores the W register
• Stores the STATUS register in Bank 0
• Executes the ISR code
• Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 9-1: SAVING THE STATUS AND
W REGISTERS IN RAM
MOVWF W_TEMP ;copy W to temp register,
;could be in either bank
SWAPF STATUS,W ;swap st atus to be saved into W
BCF STATUS,RP 0 ;change to bank 0 regardless
;of current bank
MOVWF STATUS_TEMP ;save status to bank 0
;register
:
: (ISR)
:
SWAPF STATUS_TEMP,W ;swap STATUS_TEMP regist er
;into W, sets bank to or igina l
;state
MOVWF STATUS ;move W into STATUS register
SWAPF W_TEMP,F ;swap W_TEM P
SWAPF W_TEMP,W ;swap W_TEMP into W
9.7 Watchdog Timer (WDT)
The W atchdog T imer is a free running on-chip RC oscil-
lator which does not require any extern al components.
This RC oscillator is separate from the RC oscillator of
the CL KIN pin. T hat me ans th at the W DT wil l run, e v e n
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wa ke-up an d continu e with normal o peration. T he WDT
can be permanently disab led b y prog ramm ing the co n-
figuration bit WDTE as clear (Section 9.1).
9.7.1 WDT PERIOD
The WDT ha s a nominal time-o ut period of 18 ms, (w ith
no prescaler). The time-out periods vary with tempera-
ture, VDD and proces s variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the pos tscaler , if assi gned to the WDT, and pre ve nt
it from timing out and generating a device RESET.
The TO bit in the STATUS register w ill be cle ared upo n
a Watchdog Timer tim e-ou t.
9.7.2 WDT PROGRAMMING CONSIDERATIONS
It sho uld also be tak en in acco unt that under wo rst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
PIC16C62X
DS30235H-page 58 1999 Microchip Technology Inc.
FIGURE 9-18: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
V alue on al l
other
Resets
2007h Config. bits —BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 — —
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded cells are not used by the Watchdog Timer.
Note: _ = Unimplemented location, read as “0”
+ = Reserved for future use
From TMR0 Clock Source
(Figure 6-6)
To TMR0 (Figure 6-6)
Postscaler
Watchdog
Timer
M
U
X
PSA
8 - to -1 MUX
PSA
WDT
Time-out
1
0
0
1
WDT
Enable Bit
PS<2:0>
•
•
Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
8
MUX
1999 Microchip Technology Inc. DS30235H-page 59
PIC16C62X
9.8 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
tur ned off. The I/O por ts ma intai n the sta tus th ey had,
before SLEEP was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, all I/O
pins sh ould be either at VDD or VSS with no e xternal cir-
cuitry dra wi ng cu rrent from t he I/O pi n and the co mp ar-
ators and VREF should be disabled. I/O pins that are
hi-impe dance inputs should be pulle d high or low e xter-
nally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS
for lowest current consumption. The contribution from
on chip pull-ups on PO RTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
9.8.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. Exter nal reset input on MCLR pin
2. Watchdog Timer W ake-up (if WDT w as enabled)
3. Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
The first event will cause a device reset. The two latter
events are considered a continuation of program exe-
cution. Th e T O and PD bit s in the STATUS reg ister ca n
be used to determine the cause of device reset. PD
bit, which is set on power-up, is cleared when SLEEP
is invoked. TO bit is cleared if WDT wake-up occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to w ake-up throug h an int errupt event, the co rres pon d-
ing interrupt en able b it must be set (enabl ed). W ak e-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
ru pt ad dress (00 04h ). In ca ses wh ere the execution of
the instruction following SLEEP is not desirable, the
user shoul d hav e an NOP after the SLEEP instruction.
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
Note: It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
Note: If the global interrupts are disabled (GIE is
cleared ), but any in terrupt s ourc e h as bo th
its inte rrupt en able bit and t he co rres pon d-
ing interrupt flag bits set, the device will
immediately wake-up from sleep. The
sleep instruction is completely executed.
FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
Tost(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
Note 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
Note 3: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
Note 4: CLKOUT is not available in these osc modes, but shown here for timing reference.
PIC16C62X
DS30235H-page 60 1999 Microchip Technology Inc.
9.9 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verific ati on purposes .
9.10 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during program/verify. Only the
least significant 4 bits of the ID locations are used.
Note: Microchip does not recommend code
prote cti ng wind o wed devices .
9.11 In-Circuit Serial Programming
The PIC16C62X microcontrollers can be serially
prog ram med wh ile i n the end ap plica tion c ircui t. This is
simply d one with two line s for cl ock and data a nd thre e
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the de vice , depending if th e
comma nd w as a load or a re ad. For complete deta ils of
serial programming, please refer to the
PIC16C6X/7X/9XX Programming Specification
(#DS30228).
A typical in-circuit serial programming connection is
shown in Figure 9 -20.
FIGURE 9-20: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16C62X
VDD
VSS
MCLR/VPP
RB6
RB7
+5V
0V
VPP
CLK
Data I/O
VDD
1999 Microchip Technology Inc. DS30235H-page 61
PIC16C62X
10.0 INSTRUCTION SET SUMMARY
Each PIC16C62X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16C62X instruc-
tion set summary in Table 10-2 lists byte-oriented,
bit-oriented, and literal and control operations.
Table 10-1 shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file
register designator and ’d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W registe r . If ’d ’ is one , the result i s placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
design ator which selects the n um ber of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
eigh t or eleven bit co nstant or literal value.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon’t care location (= 0 or 1)
The assembler will generat e code with x = 0. I t is t he
recommended f orm of use for compatibility with all
Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label Label name
TOS Top of Stack
PC Program Counter
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
PD Power-down bit
dest Destination either the W register or the specified
register file location
[ ] Options
( ) Contents
→Assigned to
< > Regis ter bit field
∈In the set of
i
talics
User defined term (font is courier)
The instruction set is highly orthogonal and is grouped
into three basic categories:
•Byte-oriented ope ra tio ns
•Bit-oriented operations
•Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instr uc tio n cycl es with the seco nd cy cle execu ted as a
NOP. One instruction cycle consists of four oscillator
periods . Thus, f or an oscillator frequency of 4 MHz, the
normal instruction execution time is 1 µs. If a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Table 10-1 lists the instructions recognized by the
MPASM assembler.
Figure 10-1 shows the three general formats that the
instructions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future PICmicro® products, do not use the
OPTION and TRIS instructions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16C62X
DS30235H-page 62 1999 Microchip Technology Inc.
TABLE 10-2: PIC16C62X INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Compleme nt f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip i f Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERAT IONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move lit eral to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves . For example, if the data latch is ’1’ for a pin configured as input and is driv en low by an external
devi ce , the data will be written back with a ’0’.
Note 2: If this instruction is e x ecuted on the T MR0 register (and, where applicable , d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
Note 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1999 Microchip Technology Inc. DS30235H-page 63
PIC16C62X
10.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [
label
] ADDLW k
Operands: 0 ≤ k ≤ 255
Operat ion: (W) + k → (W)
Status Affected: C, DC, Z
Encoding: 11 111x kkkk kkkk
Desc ription: T he contents of the W reg ister are
added to th e eight bit liter al ’ k’ and
the resul t is plac ed in th e W regis-
ter.
Words: 1
Cycles: 1
Example ADDLW 0x15
Before Instruction
W = 0x10
After Instruction
W = 0x25
ADDWF Add W and f
Syntax: [
label
] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (dest)
Status Affected: C, DC, Z
Encoding: 00 0111 dfff ffff
Desc ription: Add the contents of the W reg ister
with regis ter ’f’ . If ’d ’ is 0, the res ult
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
Words: 1
Cycles: 1
Example ADDWF FSR, 0
Before Instruction
W = 0x17
FSR = 0xC2
After Instruction
W= 0xD9
FSR = 0xC2
ANDLW AND Litera l with W
Syntax: [
label
] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Encoding: 11 1001 kkkk kkkk
Description: The contents of W register are
AND’ed with the eig ht bit literal 'k'.
The result is placed in the W reg-
ister.
Words: 1
Cycles: 1
Example ANDLW 0x5F
Before Instruction
W= 0xA3
After Instruction
W = 0x03
ANDWF AND W with f
Syntax: [
label
] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (dest)
Status Affected: Z
Encoding: 00 0101 dfff ffff
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W r egi ster. If 'd' i s 1, the res ult
is stored back in register 'f'.
Words: 1
Cycles: 1
Example ANDWF FSR, 1
Before Instruction
W = 0x17
FSR = 0xC2
After Instruction
W = 0x17
FSR = 0x02
PIC16C62X
DS30235H-page 64 1999 Microchip Technology Inc.
BCF Bit Clear f
Syntax: [
label
] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Encoding: 01 00bb bfff ffff
De scription: Bit ’b’ in register ’f’ is c leared.
Words: 1
Cycles: 1
Example BCF FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BSF Bit Set f
Syntax: [
label
] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Encoding: 01 01bb bfff ffff
De scription: Bit ’b’ in register ’f’ is s et.
Words: 1
Cycles: 1
Example BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
BTFSC Bit Test, Skip if Clear
Syntax: [
label
] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 01 10bb bfff ffff
Description: If bit ’b’ in register ’f’ is ’0’, then the
next instruction is skipped .
If bit ’b’ is ’0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a two-c ycle instruction.
Words: 1
Cycles: 1(2)
Example HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CO
DE
Before Instruction
PC = address HERE
After Instruction
if FLAG <1> = 0,
PC = address TRUE
if FLAG <1>= 1 ,
PC = address FALSE
1999 Microchip Technology Inc. DS30235H-page 65
PIC16C62X
BTFSS Bit Test f, Skip if Set
Syntax: [
label
] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 01 11bb bfff ffff
De scription: If bit ’b’ in regis ter ’f’ is ’1’, then the
next instruct ion is skipped.
If bit ’b’ is ’1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
Words: 1
Cycles: 1(2)
Example HERE
FALSE
TRUE
BTFSS
GOTO
•
•
•
FLAG,1
PROCESS_CO
DE
Before Instruction
PC = address HERE
After Instruction
if FLA G<1> = 0,
PC = address FALSE
if FLA G<1> = 1,
PC = address TRUE
CALL Call Subroutine
Syntax: [
label
] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Encoding: 10 0kkk kkkk kkkk
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate addre ss is loaded into PC bi ts
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
Words: 1
Cycles: 2
Example HERE CALL
THER
E
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
CLRF Clear f
Syntax: [
label
] CLRF f
Operands: 0 ≤ f ≤ 127
Operat ion: 00h → (f)
1 → Z
Status Affected: Z
Encoding: 00 0001 1fff ffff
Description: The contents of register ’f’ are
cleared and the Z bit is set.
Words: 1
Cycles: 1
Example CLRF FLAG_REG
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
Z=1
PIC16C62X
DS30235H-page 66 1999 Microchip Technology Inc.
CLRW Clear W
Syntax: [
label
] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Encoding: 00 0001 0000 0011
Description: W register is cleared. Zero bit (Z)
is set.
Words: 1
Cycles: 1
Example CLRW
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z=1
CLRWDT Clear Watchdog Timer
Syntax: [
label
] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0100
Description: CLRWDT instruction resets the
W atchdog Timer . It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
Words: 1
Cycles: 1
Example CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0 x00
WDT prescaler= 0
TO =1
PD =1
COMF Complement f
Syntax: [
label
] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (dest)
Status Affected: Z
Encoding: 00 1001 dfff ffff
Description: The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is sto r ed in W. If ’ d’ is 1, the
result is stored back in register ’f’.
Words: 1
Cycles: 1
Example COMF REG1,0
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
W=0xEC
DECF Decrement f
Syntax: [
label
] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (dest)
Status Affected: Z
Encoding: 00 0011 dfff ffff
Description: Decrement register ’f’. If ’d’ is 0,
the result is sto red in the W regis -
ter. If ’d’ is 1, the result is stored
back in r egister ’f’.
Words: 1
Cycles: 1
Example DECF CNT, 1
Before Instruction
CNT = 0x01
Z=0
After Instruction
CNT = 0x00
Z=1
1999 Microchip Technology Inc. DS30235H-page 67
PIC16C62X
DECFSZ Decrement f, Skip if 0
Syntax: [
label
] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation : (f) - 1 → (dest); skip if result = 0
Status Affected: None
Encoding: 00 1011 dfff ffff
Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 0, the next instruc-
tion, which is already fetched, is
disc arde d. A NOP is execut ed
instead making it a two-cycle
instruction.
Words: 1
Cycles: 1(2)
Example HERE DECFSZ CNT, 1
GOTO LOOP
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
CNT = CNT - 1
if CNT = 0,
PC = addres s CONTINUE
if CNT ≠0,
PC = address HERE+1
GOTO Unconditional Branch
Syntax: [
label
] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Encoding: 10 1kkk kkkk kkkk
Description: GOTO is an unconditional branch.
The eleven bi t immed iate val ue is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
Words: 1
Cycles: 2
Example GOTO THERE
After Instruction
PC = Address THERE
INCF Increm ent f
Syntax: [
label
] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (dest)
Status Affected: Z
Encoding: 00 1010 dfff ffff
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
Words: 1
Cycles: 1
Example INCF CNT, 1
Before Instruction
CNT = 0xFF
Z=0
After Instruction
CNT = 0x00
Z=1
PIC16C62X
DS30235H-page 68 1999 Microchip Technology Inc.
INCFSZ Increment f, Skip if 0
Syntax: [
label
] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (dest), skip if result = 0
Status Affected: None
Encoding: 00 1111 dfff ffff
Description: The contents of register ’f’ are
increm ented. If ’ d’ i s 0 the re sult is
placed in the W register. If ’d’ is 1,
the resu lt is pla ce d back in regis-
ter ’f’.
If the result is 0, the next instruc-
tion, which is already fetched, is
disc arde d. A NOP is executed
instead making it a two-cycle
instruction.
Words: 1
Cycles: 1(2)
Example HERE INCFSZ CNT, 1
GOTO LOOP
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
CNT = CNT + 1
if CNT= 0,
PC = addres s CONTINUE
if CNT≠0,
PC = address HERE +1
IORLW Inclusive OR Literal with W
Syntax: [
label
] IORLW k
Operands: 0 ≤ k ≤ 255
Operat ion: (W) .OR. k → (W)
Status Affected: Z
Encoding: 11 1000 kkkk kkkk
Description: The contents of the W register is
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
Words: 1
Cycles: 1
Example IORLW 0x35
Before Instruction
W = 0x9A
After Instruction
W= 0xBF
Z=1
IORWF Inclusive OR W with f
Syntax: [
label
] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (dest)
Status Affected: Z
Encoding: 00 0100 dfff ffff
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
Words: 1
Cycles: 1
Example IORWF RESULT, 0
Before Instruction
RESULT = 0x13
W = 0x91
After Instruction
RESULT = 0x13
W = 0x93
Z=1
1999 Microchip Technology Inc. DS30235H-page 69
PIC16C62X
MOVLW Move Literal to W
Syntax: [
label
] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Encoding: 11 00xx kkkk kkkk
Description: The eight bit literal ’k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
Words: 1
Cycles: 1
Example MOVLW 0x5A
After Instruction
W = 0x5A
MO VF Move f
Syntax: [
label
] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (dest)
Status Affected: Z
Encoding: 00 1000 dfff ffff
Description: The contents of register f is
mo ved to a destin ation depen dent
upon the st atus of d. If d = 0, des-
tination is W register. If d = 1, the
destin ation is fil e register f it self . d
= 1 is useful to test a file register
since status flag Z is affected.
Words: 1
Cycles: 1
Example MOVF FSR, 0
After Instruction
W = value in FSR register
Z= 1
MOVWF Move W to f
Syntax: [
label
] MOVWF f
Operands: 0 ≤ f ≤ 127
Operat ion: (W) → (f)
Status Affected: None
Encoding: 00 0000 1fff ffff
Description: Move data from W register to reg-
ister 'f'.
Words: 1
Cycles: 1
Example MOVWF OPTION
Before Instruction
OPTION = 0xFF
W = 0x4F
After Instruction
OPTION = 0x4F
W = 0x4F
NOP No Operation
Syntax: [
label
] NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 00 0000 0xx0 0000
Description: No operation.
Words: 1
Cycles: 1
Example NOP
PIC16C62X
DS30235H-page 70 1999 Microchip Technology Inc.
OPTION Load Option Register
Syntax: [
label
] OPTION
Operands: None
Operation: (W) → OPTION
Status Affected: None
Encoding: 00 0000 0110 0010
Description: The c ont ents of th e W reg is ter are
loaded in the OPTION register.
This instruction is supported for
code compatibility with PIC16C5X
prod uct s . Si nce O PTION is a read-
able/writable register, the user can
directly address it.
Words: 1
Cycles: 1
Example To maintain upward compatibility
with future PICmicro® products, do
not use this instruct i on.
RETFIE Return from Interrupt
Syntax: [
label
] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affected: None
Encoding: 00 0000 0000 1001
Description: Return from Interrupt. Stack is
POPed and Top of Stack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global Inter-
rupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with Literal in W
Syntax: [
label
] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Encoding: 11 01xx kkkk kkkk
Description: The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words: 1
Cycles: 2
Example
TABLE
CALL TABLE;W contains table
;offset value
• ;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [
label
] RETURN
Operands: None
Operation: TOS → PC
Status Affected: None
Encoding: 00 0000 0000 1000
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
Words: 1
Cycles: 2
Example RETURN
After Interrupt
PC = TOS
1999 Microchip Technology Inc. DS30235H-page 71
PIC16C62X
RLF Rotate Left f through Carry
Syntax: [
label
] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Encoding: 00 1101 dfff ffff
Description: The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’ d’ is 0, the re sult
is place d in th e W regi ste r. If ’ d’ is
1, the result is stored back in reg-
ister ’f’.
Words: 1
Cycles: 1
Example RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W= 1100 1100
C=1
Register fC
RRF Rotate Right f through Carry
Syntax: [
label
] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Encoding: 00 1100 dfff ffff
Description: The contents of register ’f’ are
rotated on e bit to the right throu gh
the Ca rry Flag. If ’ d’ is 0, the resu lt
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
Words: 1
Cycles: 1
Example RRF REG1,
0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W= 0111 0011
C=0
SLEEP
Syntax: [
label
]SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0011
Description: The power-down status bit, PD
is cleared. Time-out status bit,
TO is set. Watchdog Timer and
its pres ca ler are cle are d.
The processor is put into SLEEP
mode with the oscillator
stopped. See Section 9.8 for
more detail s .
Words: 1
Cycles: 1
Example: SLEE
P
Register fC
PIC16C62X
DS30235H-page 72 1999 Microchip Technology Inc.
SUBLW Subtract W from Literal
Syntax: [
label
]SUBLW k
Operan ds: 0 ≤ k ≤ 255
Operatio n: k - (W) → (W)
Status
Affected: C, DC, Z
Encoding: 11 110x kkkk kkkk
Description: The W register is subtracted (2’s
complement method) from the eight
bit literal 'k'. The result is placed in
the W reg ister.
Words: 1
Cycles: 1
Example 1: SUBLW 0x02
Before Instruction
W= 1
C=?
After Instruction
W= 1
C = 1; result is positive
Example 2: Before Instruction
W= 2
C=?
After Instruction
W= 0
C = 1; result is zero
Example 3: Before Instruction
W= 3
C=?
After Instruction
W= 0xFF
C = 0; result is negative
SUBWF Subtract W from f
Syntax: [
label
]SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (dest)
Status
Affected: C, DC, Z
Encoding: 00 0010 dfff ffff
Description: Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W register.
If 'd' is 1, the result is stored back in
register 'f'.
Words: 1
Cycles: 1
Example 1: SUBW
FREG1,1
Before Inst ruction
REG1 = 3
W=2
C=?
After Instruction
REG1 = 1
W=2
C = 1; result is positive
Example 2: Before Instruction
REG1 = 2
W=2
C=?
After Instruction
REG1 = 0
W=2
C = 1; result is zero
Example 3: Before Instruction
REG1 = 1
W=2
C=?
After Instruction
REG1 = 0xFF
W=2
C = 0; result is negative
1999 Microchip Technology Inc. DS30235H-page 73
PIC16C62X
SWAPF Swap Nibbles in f
Syntax: [
label
] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (dest<7:4>) ,
(f<7:4>) → (dest<3 :0>)
Status Affected: None
Encoding: 00 1110 dfff ffff
Description: The upper and lower nibbles of
register ’f’ are exchanged. If ’d’ is
0, the result is placed in W regis-
ter. If ’ d’ is 1, the result is plac ed in
register ’f’.
Words: 1
Cycles: 1
Example SWAPF REG, 0
Before Instruction
REG1 = 0xA5
After Instruction
REG1 = 0xA5
W = 0x5A
TRIS Load TRIS Register
Syntax: [
label
] TRIS f
Operands: 5 ≤ f ≤ 7
Operation: (W) → TRIS register f;
Status Affected: None
Encoding: 00 0000 0110 0fff
Description: The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and writ-
able, the user can directly address
them.
Words: 1
Cycles: 1
Example To maintain upward compatibility
with future PICmicro® products, do
not use this instruct i on.
XORLW Exclusive OR Literal with W
Syntax: [
label
]XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Encoding: 11 1010 kkkk kkkk
Description: The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
Words: 1
Cycles: 1
Example: XORL
W0xAF
Before Instruction
W= 0xB5
After Instruction
W = 0x1A
XORWF Exclusive OR W with f
Syntax: [
label
] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (dest)
Status Affected: Z
Encoding: 00 0110 dfff ffff
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stor ed back in regis ter 'f'.
Words: 1
Cycles: 1
Example XORW
FREG 1
Before Instruction
REG = 0xAF
W=0xB5
After Instruction
REG = 0x1A
W=0xB5
PIC16C62X
DS30235H-page 74 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 75
PIC16C62X
11.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full r an ge of hardw are and softw are d e velopment to ols:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
- MPLAB-SIM Software Simulator
•Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circui t
Emulator
-ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
-PRO MATE
II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
-KEELOQ
11.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows-based applica-
tion which contains:
• Multiple functionality
-editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
• On-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
proje ct information)
• Debug using:
- source files
- abs olute listing file
- object code
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a c on si ste nt pl atform and the abi l-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
11.2 MPASM Assembler
MPASM is a full f eatured unive rsal macr o assembl er for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and c an be u sed a s a stand alone appli catio n o n a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file w hi ch con t ai ns so urce li nes an d gen-
erated machine code, and a COD file for MPLAB
debugging.
MPASM feature s includ e:
• MPASM and MPLINK are integrated into MPLAB
projects.
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directiv es a llow c omplete c ontrol o ve r the
assem b l y proces s .
11.3 MPL AB-C17 and MPLAB-C18
C Compilers
The MPLAB-C 17 and MPLAB -C18 Code De v elop ment
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other co mpi le rs .
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC16C62X
DS30235H-page 76 1999 Microchip Technology Inc.
11.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows l arg e li brarie s t o b e use d e ffi ci en tl y i n ma ny di f-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLINK features include:
• MPLINK wor ks with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features include:
• MPLIB makes link ing easier bec ause singl e li brar-
ies can be included instead of many smaller files.
• MPLIB hel ps k ee p code maintai nab le by groupin g
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
11.5 MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level . On any given in struct ion, th e data areas ca n be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
e xecution can be perf ormed in sin gle step , ex ecute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
deb ug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
11.6 MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
inte nded to provi de t he pr oduc t developm ent en gin eer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platf orm and Microsoft® Windows
3.x/95/98 environment w ere chosen to best make these
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
11.7 PICMASTER/PIC MASTER CE
The PICMASTER system from Microchip Technolog y is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
11.8 ICEPIC
ICEPIC is a lo w-cost in-circ uit emula tion solution f o r the
Microchip Technology PIC16 C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX fam ilies of 8-bit on e-time-
progr amma b le (OTP) microcontrollers. The modula r
system can suppo rt different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeab le persona lity modules or daughter
boards. The em ulator is capable of emulating without
target application circuitry being present.
11.9 MPLAB-ICD In-Circuit Debugger
Microc hip’s In-C ircuit Deb ugger , MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F8 7X. This f eature, alon g with Microchip’ s In-C ir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
de velop and deb ug so urce c ode b y w atchi ng v ariab les ,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
1999 Microchip Technology Inc. DS30235H-page 77
PIC16C62X
11.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
ture d programme r capable of operati ng in stand -alo ne
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to suppor t various package types. In
stand-al on e m ode the PRO MATE II can read , verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
11.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supp o rts a ll P ICmi cro device s wit h up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
11.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Mi cro chip’s PIC12C5XX, PIC12CE5 XX, an d
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non- real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system . In addition, the target system can provi de input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
11.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and downl o a d t h e
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
11.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTAR T-Plus , and eas ily tes t firmware .
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional ha rdware and connectin g it to the mic rocontroll er
soc ket (s). Some of the f eatures include a RS-232 int er-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of th e I2C bu s and separ ate hea ders f or connec -
tion to an LCD module and a keypad.
11.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microc ont roll ers wi th a LCD Mo dul e . All the neces -
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDE M- 3 boa rd, on a PRO MATE II pr ogram-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Addition al pr ototyp e are a has bee n pr ovided t o
the us er for adding ha rdware and con necti ng it to the
microcontroller sock et(s). Some of the f eatures inc lude
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a k e y pad. Als o pro vide d on th e PICDEM -3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the w e ek . Th e P I CD EM-3 provides a n addi-
tional RS-232 interface and Windows 3.1 software for
showing the dem ultiplex ed LCD signals on a PC . A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
PIC16C62X
DS30235H-page 78 1999 Microchip Technology Inc.
11.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers, including PIC17C752, PIC17C756,
PIC17C762, and PIC17C766. All necessar y hardware
is incl uded to run bas ic demo prog rams, which are su p-
plied on a 3.5-inch disk. A programmed sample is
includ ed, and the us er ma y eras e it an d prog ram it wi th
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code . In additio n, PICDEM-17 su p-
ports down-loa ding of progr ams to and e xec uting out of
e xt ernal FLASH memory on board. The PICD EM -17 i s
also usab le with th e MPL AB-ICE or PI CMASTER em u-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
11.17 SEEV AL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes ever ything necessar y to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analy sis a nd relia bility calc ulatio ns . The tota l kit ca n
significantly reduce time-to-market and result in an
optimized system.
11.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microc hips HCS Secure D ata Product s. The HC S ev al-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
1999 Microchip Technology Inc. DS30235H-page 79
PIC16C62X
TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Software Tools
MPLAB® Integrated
Development Environment
á
á
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB® C17 Compiler
á
á
MPLAB® C18 Compiler
á
MPASM/MPLINK
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Emulators
MPLAB®-ICE
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PICMASTER/PICMASTER-CE
á
á
á
á
á
á
á
á
á
á
á
ICEPIC Low-Cost
In-Circu it Emulator
á
á
á
á
á
á
á
á
Debugger
MPLAB®-ICD In-Circuit
Debugger
á
*
á
*
á
Programmers
PICSTARTPlus
Low-Cost Universal Dev. Kit
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PRO MATE II
Universal Programmer
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
á
á
Demo Boards and Eval Kits
SIMICE
á
á
PICDEM-1
á
á
á
†
á
á
PICDEM-2
á
†
á
†
á
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
KEELOQ® Evaluation Kit
á
KEELOQ Transponder Kit
á
microID™ Programmer’s Kit
á
125 kHz microID Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
13.56 MHz Anticollision microID
Developer’s Kit
á
MCP2510 CAN Developer’s Kit
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB®-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC16C62X
DS30235H-page 80 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 81
PIC16C62X
12.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings †
Ambient Temperature under bias................................... ..... ....................... ..... ....................... ..... .............. -40° to +125°C
Storage Temperature ................................................................................................................................ -65° to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)........................................................-0.6V to VDD +0.6V
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Voltage on RA4 with respect to VSS...........................................................................................................................8.5V
Total power Dissipation (Note 1)...............................................................................................................................1.0W
Maximum Curre nt out of VSS pin...........................................................................................................................300 mA
Maximum Current into VDD pin .............................................................................................................................250 mA
Input Clamp Current, IIK (VI <0 or VI> VDD)......................................................................................................................±20 mA
Output Clamp Current, IOK (VO <0 or VO>VDD)................................................................................................................±20 mA
Maximum Output Current sunk by any I/O pin........................................................................................................25 mA
Maximum Output Current sourced by any I/O pin...................................................................................................25 mA
Maximum Current sunk by PORTA and PORTB ...................................................................................................200 mA
Maximum Current sourced by PORTA and PORTB..............................................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spi kes belo w VSS at the MCLR pin, inducing curren ts greater than 80 mA, m ay c ause latch-up . T hus,
a series resistor of 50-100Ω should be use d w hen a ppl ying a "l o w " l evel to the MC L R pin r ather tha n pullin g
this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operatio n listings of this s pecification is not implied. Exposure to maximum rating c onditions
for extended periods may affect device reliability.
PIC16C62X
DS30235H-page 82 1999 Microchip Technology Inc.
FIGURE 12-1: PIC16C62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
FIGURE 12-2: PIC16LC6 2X VOLTAGE-FR EQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1999 Microchip Technology Inc. DS30235H-page 83
PIC16C62X
FIGURE 12-3: PIC16C62XA VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
FIGURE 12-4: PIC16C62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ 0°C, +70°C ≤ TA ≤ +125°C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC16C62X
DS30235H-page 84 1999 Microchip Technology Inc.
FIGURE 12-5: PIC16LC62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
FIGURE 12-6: PIC16CR62XA VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(VOLTS)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1999 Microchip Technology Inc. DS30235H-page 85
PIC16C62X
FIGURE 12-7: PIC16CR62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ 0°C,
+70°C ≤ TA ≤ +1 25°C
FIGURE 12-8: PIC16LCR62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(VOLTS)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC16C62X
DS30235H-page 86 1999 Microchip Technology Inc.
12.1 DC CHARACTERISTICS: PIC16C62X-04 (Commercial, Industrial, Extended)
PIC16C62X-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C≤ TA ≤ +85°C for indus trial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ† Ma
xUnit
sConditions
D001 VDD Supply Voltage 3.0 – 6.0 V See Figures 12-1 through 12-5
D002 VDR RAM Data Retention Voltage
(Note 1) – 1.5* – V De vice in SLEEP mode
D003 VPOR VDD start voltage to
ensure Power-on Reset – Vss – V See section on power-on reset for details
D004 SVDD VDD rise rate to ensure
Power-on Reset 0.05* – – V/ms See section on power-on reset for details
D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.3 V BOREN configuration bit is cleared
D010 IDD Supply Current (Note 2) –
–
–
1.8
35
9.0
3.3
70
20
mA
µA
mA
FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT
mode, (Note 4)*
FOSC = 32 kHz, VDD = 4.0V, WDT disabled, LP
mode
FOSC = 20 MHz, VDD = 5.5V, WDT disabled, HS
mode
D020 IPD Power Down Current (Note 3) – 1.0 2.5
15 µA
µAVDD=4.0V, WDT disabled
(125°C)
D022
D022A
D023
D023A
∆IWDT
∆IBOR
∆ICOMP
∆IVREF
WDT Current (Note 5)
Brown-out Reset Current (Note 5)
Comparator Current for each
Comparator (Note 5)
VREF Current (Note 5)
–
–
–
–
6.0
350
20
25
425
100
300
µA
µA
µA
µA
µA
VDD=4.0V
(125°C)
BOD enabled, VDD = 5.0V
VDD = 4.0V
VDD = 4.0V
1A FOSC LP Oscillator Operating
Frequency
RC Oscillator Operating
Frequency
XT Oscillator Operating
Frequency
HS Oscillator Operating
Frequency
0
0
0
0
–
–
–
–
200
4
4
20
kHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = exter nal square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
for mula: Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this per ipheral is enabled. This current should be added to the
base IDD or IPD measurement.
1999 Microchip Technology Inc. DS30235H-page 87
PIC16C62X
12.2 DC CHARACTERISTICS: PIC16LC62X-04 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Oper ati ng tem per a t ure –40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
Oper ati ng voltag e VDD range as described in DC spec Table 12-1
Para
m
No.
Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 2.5 – 6.0 V See Figures 12-1 through 12-5
D002 VDR RAM Data Retention Voltage (Note 1) – 1.5* – V Device in SLEEP mode
D003 VPOR VDD start voltage to
ensure Power-on Reset –VSS – V See section on Power-on Reset for details
D004 SVDD VDD ri se rate to ensure
Power-on Reset 0.05* – – V/ms See section on Power-on Reset for details
D005 VBOR Brown-out Detect Voltage 3.7 4. 0 4.3 V BOREN configuration bit is cleared
D010 IDD Supply Current (Note 2) –
–
1.4
26
2.5
53
mA
µA
FOSC = 2.0MHz, VDD = 3.0V, WDT dis-
abled, XT mode, (Note 4)
FOSC = 32kHz, VDD = 3.0V, WD T disab led,
LP mode
D020 IPD Power Down Current (Note 3) – 0.7 2 µAVDD=3.0V, WDT disabled
D022
D022A
D023
D023A
∆IWDT
∆IBOR
∆ICOMP
∆IVREF
WDT Current (Note 5)
Brown-out Reset Current (Note 5)
Comparator Current for each
Comparator (Note 5)
VREF Current (Note 5)
–
–
–
–
6.0
350 15
425
100
300
µA
µA
µA
µA
VDD=3.0V
BOD ena bled , VDD = 5.0V
VDD = 3.0V
VDD = 3.0V
1A FOSC LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
–
–
–
–
200
4
4
20
kHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are f or design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating volt age and frequency. Other f actors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption. The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O p ins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD to VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
for mula: Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enab led. This current should be added to the base
IDD or IPD measurement.
PIC16C62X
DS30235H-page 88 1999 Microchip Technology Inc.
12.3 DC CHARACTERISTICS: PIC16C62XA-04 (Commercial, Industrial, Extended)
PIC16C62XA-20 (Commercial, Industrial, Extended)
* These parameters are characterized but not tested.
† Data in " Typ" column is at 5.0V, 25 °C , unless otherwise stated. These parameters are f or design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = exter nal square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power do wn current in SLEEP mode does not depend on the oscillator type . Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
for mula: Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
6: Commercial temperature range only.
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 3.0 - 5.5 V See Figures 12-1 through 12-5
D002 VDR RAM Data Retention
Voltage (Note 1) – 1.5* – V Device in SLEEP mode
D003 VPOR VDD start voltage to
ensure Power-on Reset –VSS – V See section on power-on reset for details
D004 SVDD VDD rise rate to ensure
Power-on Reset 0.05* – – V/ms See section on power-on reset for details
D005 VBOR B rown-out Detect Voltage 3.7 4.0 4.35 V B O REN configu ration bit is cleared
D010 IDD Supply Current (Note 2, 4) –
–
–
–
–
–
1.2
0.4
1.0
4.0
4.0
35
2.0
1.2
2.0
6.0
7.0
70
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT
mode, (Note 4)*
FOSC = 4 MHz, VDD = 3.0V, WDT disabled, XT
mode, (Note 4)*
FOSC = 10 MHz, VDD = 3.0V, WDT disabled, HS
mode, (Note 6)
FOSC = 20 MHz, VDD = 4.5V, WDT disabled, HS
mode
FOSC = 20 MHz, VDD = 5.5V, WDT disabled*, HS
mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP
mode
D020 IPD Power Down Current (Note 3) –
–
–
–
–
–
–
–
2.2
5.0
9.0
15
µA
µA
µA
µA
VDD = 3.0V
VDD = 4.5V*
VDD = 5.5V
VDD = 5.5V Extended Temp.
D022
D022A
D023
D023A
∆IWDT
∆IBOR
∆ICOMP
∆IVREF
WDT Current (N ote 5)
Brown-out Reset Current (Note
5)
Comparator Current for each
Comparator (Note 5)
VREF Current (Note 5)
–
–
–
–
6.0
75
30
80
10
12
125
60
135
µA
µA
µA
µA
µA
VDD = 4.0V
(125°C)
BOD enabled, VDD = 5.0V
VDD = 4.0V
VDD = 4.0V
1A FOSC LP Oscillator Operating Frequency
RC Oscillator Operating F requency
XT Oscillator Operating Frequency
HS Oscillator Operating F r equency
0
0
0
0
—
—
—
—
200
4
4
20
kHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
1999 Microchip Technology Inc. DS30235H-page 89
PIC16C62X
12.4 DC CHARACTERISTICS: PIC16LC62XA-04 (Commercial, Industrial, Extended)
* These parameters are characterized but not tested.
† Data in " Typ" column is at 5.0V, 25 °C , unless otherwise stated. These parameters are f or design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating volt age and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active oper ati on mode are:
OSC1 = exter nal square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power do wn current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
for mula: Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
6: Commercial temperature range only.
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Oper ati ng tem perature –40°C≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 2.5 - 5.5 V See Figures 12-1 through 12-5
D002 VDR RAM Data Retention
Voltage (Note 1) – 1.5* – V Device in SLEEP mode
D003 VPOR VDD start voltage to
ensure Power-on Reset –VSS – V See section on power-on reset for details
D004 SVDD VDD rise rate to ensure
Power-on Reset 0.05* – – V/ ms See section on power-on reset for details
D005 VBOR Brown-out Detect Voltage 3.7 4. 0 4.35 V BOREN configuration bit is cleared
D010 IDD Supply Current (Note 2) –
–
–
1.2
–
35
2.0
1.1
70
mA
mA
µA
FOSC = 4MHz, VDD = 5.5V, WDT disabled, XT
mode, (Note 4)*
FOSC = 4MHz, VDD = 2.5V, WDT disabled, XT
mode, (Note 4)
FOSC = 32kHz, VDD = 2.5V, WDT disab led, LP
mode
D020 IPD Power Down Current (Note 3) –
–
–
–
–
–
–
–
2.0
2.2
9.0
15
µA
µA
µA
µA
VDD = 2.5V
VDD = 3.0V*
VDD = 5.5V
VDD = 5.5V Extended Tem p.
D022
D022A
D023
D023A
∆IWDT
∆IBOR
∆ICOMP
∆IVREF
WDT Current (Note 5)
Brown-out Reset Current
(Note 5)
Comparator Current for each
Comparator (Note 5)
VREF Current (Note 5)
–
–
–
–
6.0
75
30
80
10
12
125
60
135
µA
µA
µA
µA
µA
VDD=4.0V
(125°C)
BOD enabled, VDD = 5.0V
VDD = 4.0V
VDD = 4.0V
1A FOSC LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
20
kHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
PIC16C62X
DS30235H-page 90 1999 Microchip Technology Inc.
12.5 DC CHARACTERISTICS: PIC16CR62XA-04 (Commercial, Industrial, Extended)
PIC16CR62XA-20 (Commercial, Industrial, Extended)
* These parameters are characterized but not tested.
† Data in " Typ" column is at 5.0V, 25 °C , unless otherwise stated. These parameters are f or design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = exter nal square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power do wn current in SLEEP mode does not depend on the oscillator type . Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
for mula: Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
6: Commercial temperature range only.
DC CHARACTERISTICS
Standard Operating Conditions (unle ss otherwis e stated )
Operating temperature –40°C≤ TA ≤ +85°C for indu strial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 2.5 - 5.5 V See Figures 12-1 through 12-5
D002 VDR RAM Data Retention
Voltage (Note 1) – 1.5* – V Device in SLEEP mode
D003 VPOR VDD start voltage to
ensure Power-on Reset –VSS – V See section on power-on reset for details
D004 SVDD VDD rise rate to ensure
Power-on Reset 0.05* – – V/ms See section on power-on reset f or details
D005 VBOR B rown-out Detect Voltage 3.7 4.0 4.35 V B O REN conf iguration bit is cleared
D010 IDD Supply Current (Note 2) –
–
–
–
–
–
1.2
–
–
4.0
–
35
2.0
1.2
2.0
7.0
6.0
70
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT
mode, (Note 4)*
FOSC = 4 MHz, VDD = 3.0V, WDT disabled, XT
mode, (Note 4)
FOSC = 10 MHz, VDD = 3.0V, WDT disabled, HS
mode, (Note 6)
FOSC = 20 MHz, VDD = 5.5V, WDT disabl ed*, HS
mode
FOSC = 20 MHz, VDD = 4.5V, WDT disabled, HS
mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP
mode
D020 IPD Power Down Current (Note 3) –
–
–
–
–
–
–
–
2.2
5.0
9.0
15
µA
µA
µA
µA
VDD = 3.0V
VDD = 4.5V*
VDD = 5.5V
VDD = 5.5V Extended Temp.
D022
D022A
D023
D023A
∆IWDT
∆IBOR
∆ICOMP
∆IVREF
WDT Current (Note 5)
Brown-out Reset Current
(Note 5)
Comparator Current for each
Comparator (Note 5)
VREF Current (Note 5)
–
–
–
–
6.0
75
30
80
10
12
125
60
135
µA
µA
µA
µA
µA
VDD=4.0V
(125°C)
BOD enabled, VDD = 5.0V
VDD = 4.0V
VDD = 4.0V
1A FOSC LP Oscillator Operating F requency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
20
kHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
1999 Microchip Technology Inc. DS30235H-page 91
PIC16C62X
12.6 DC CHARACTERISTICS: PIC16LCR62XA-04 (Commercial, Industrial, Extended)
* These parameters are characterized but not tested.
† Data in " Typ" column is at 5.0V, 25 °C , unless otherwise stated. These parameters are f or design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating volt age and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active oper ati on mode are:
OSC1 = exter nal square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power do wn current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
for mula: Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
6: Commercial temperature range only.
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C≤ TA ≤ +85°C for indu strial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C≤ TA ≤ +125°C for extended
Para
m
No.
Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 2.0 - 5.5 V See Figures 12-1 through 12-5
D002 VDR RAM Data Retention
Voltage (Note 1) – 1.5* – V De vice in SLEEP mode
D003 VPOR VDD start voltage to
ensure Power-on Reset –VSS – V See section on power-on reset for details
D004 SVDD VDD rise rate to ensure
P ower-on Reset 0.05* – – V/ms See section on power-on reset for details
D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.35 V BOREN configuration bit is cleared
D010 IDD Supply Current (Note 2) –
–
–
1.2
–
35
2.0
1.1
70
mA
mA
µA
FOSC = 4.0 MHz, VDD = 5.5V, WDT disabled,
XT mode, (Note 4)*
FOSC = 4.0 MHz, VDD = 2.5V, WDT disabled,
XT mode (Note 4)
FOSC = 32 kHz, VDD = 2.5V, WDT disabled,
LP mode
D020 IPD Power Down Current (Note 3) –
–
–
–
–
–
–
–
2.0
2.2
9.0
15
µA
µA
µA
µA
VDD = 2.5V
VDD = 3.0V*
VDD = 5.5V
VDD = 5.5V Extended
D022
D022A
D023
D023A
∆IWDT
∆IBOR
∆ICOMP
∆IVREF
WDT Current (Note 5)
Brown-out Reset Current
(Note 5)
Comparator Current f or each
Comparator (Note 5)
VREF Current (Note 5)
–
–
–
–
6.0
75
30
80
10
12
125
60
135
µA
µA
µA
µA
µA
VDD=4.0V
(125°C)
BOD enabled, VDD = 5.0V
VDD = 4.0V
VDD = 4.0V
1A FOSC LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
20
kHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
PIC16C62X
DS30235H-page 92 1999 Microchip Technology Inc.
12.7 DC CHARACTERISTICS: PIC16C62X/C62XA/CR62XA (Commercial, Industrial, Extended)
PIC16LC62X/LC62XA/LCR62XA (Commercial, Industrial, Extended)
DC CHARACTERI STICS
Standard Operating Conditions (unless otherwise stated)
Operating temper ature –40°C ≤ TA ≤ +85°C for indu s t r i a l an d
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 12-1
Param.
No. Sym Characteristic Min Typ† Max Unit Conditions
VIL Input Low Voltage
I/O ports
D030 with TTL buffer VSS -0.8V
0.15VDD VVDD = 4.5V to 5.5 V
otherwise
D031 with Schmitt Trigger input VSS 0.2VDD V
D032 MCLR, RA4/T0CKI,OSC1 (in RC
mode) Vss - 0.2VDD VNote1
D033 OSC1 (in XT and HS) Vss - 0.3VDD V
OSC1 (in LP) Vss - 0.6VDD-1.0 V
VIH Input High Voltage
I/O ports -
D040 with TTL buffer 2.0V
.25VDD + 0.8V -V
DD
VDD VVDD = 4.5V t o 5.5 V
otherwise
D041 with Schmitt Trigger input 0.8VDD VDD
D042 MCLR RA4/T0CKI 0.8VDD -VDD V
D043
D043A OSC1 (XT, HS and LP)
OSC1 (in RC mode) 0.7VDD
0.9VDD -VDD VNote1
D070 IPURB PORTB weak pull-up current 50 200 400 µAVDD = 5.0V, VPIN = VSS
IIL Input Leakage Current (2, 3)
I/O ports (Except PORTA) ±1.0 µAV
SS ≤ VPIN ≤ VDD, pin at hi-impedanc e
D060 PORTA - - ±0.5 µAVss
≤ VPIN ≤ VDD, pin at hi-impedance
D061 RA4/T0CKI - - ±1.0 µAVss
≤ VPIN ≤ VDD
D063 OSC1, MCLR --
±5.0 µAVss
≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL Output Low Voltage
D080 I/O ports - - 0.6 V IOL=8.5 mA, VDD=4.5V, -40° to +85°C
--0.6VI
OL=7.0 mA, VDD=4.5V, +125°C
D083 OSC2/CLKOUT (RC only) - - 0.6 V IOL=1.6 mA, VDD=4.5V, -40° to +85°C
--0.6VI
OL=1.2 mA, VDD=4.5V, +125°C
VOH Output High Voltage (3)
D090 I/O ports (Except RA4) VDD-0.7 - - V IOH=-3.0 mA, VDD=4.5V, -40° to +85°C
VDD-0.7 - - V IOH=-2.5 mA, VDD=4.5V, +125°C
D092 OSC2/CLKOUT (RC only) VDD-0.7 - - V IOH=-1.3 mA, VDD=4.5V, -40° to +85°C
VDD-0.7 - - V IOH=-1.0 mA, VDD=4.5V, +125°C
*D150 VOD Open-Drain High Voltage 10*
8.5* V RA4 pin PIC16C62X, PIC16LC62X
RA4 pin PIC16C62XA, PICLC62XA,
PIC16CR62XA, PIC16LCR62XA
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin 15 pF In XT, HS and LP modes when external
clock used to drive OSC1.
D101 CIO All I/O pins /OSC2 (in RC mode) 50 pF
* These parameters are characterized but not tested.
† Dat a i n “Typ ” co l u m n i s at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configu r ation, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C62X(A) be driv en
with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied volt age level. The specified levels repres ent normal operat -
ing conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
1999 Microchip Technology Inc. DS30235H-page 93
PIC16C62X
TABLE 12-1: COMPARATOR SPECIFICATIONS
Operat i ng C ond it i ons : V DD range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is specified in
Table 12-1.
TABLE 12-2: VOLTAGE REFERENCE SPECIFICATIONS
Operat ing Cond itions: VDD range as described in Table 12-1, -40°C<TA<+125°C. C urrent consumpt ion is s pecified in
Table 12-1.
Characteristics Sym Min Typ Max Units Comments
Input offset voltage ± 5.0 ± 10 mV
Input common mode voltage 0 VDD - 1.5 V
CMRR +55* db
Response Time(1) 150* 400*
600* ns
ns PIC16C62X(A)
PIC16LC62X
Comparator Mode Change to
Output Valid 10* µs
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD.
Characteristics Sym Min Typ Max Units Comments
Resolution VDD/24
VDD/32 LSB
LSB Low Range (V RR=1)
High Range (VRR=0)
Absolute Accuracy +1/4
+1/2 LSB
LSB Low Range (V RR=1)
High Range (VRR=0)
Unit Resistor Value (R) 2K* ΩFigure 8-1
Settling Tim e(1) 10* µs
* These parame ters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
PIC16C62X
DS30235H-page 94 1999 Microchip Technology Inc.
12.8 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
FIGURE 12-9: LOAD CONDITIONS
1. TppS2ppS
2. TppS
TFFrequency TTime
Lowercase subscripts (pp) and their meanings:
pp
ck CLKOUT osc OSC1
io I/O port t0 T0CKI
mc MCLR
Uppe rcase letters and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-Impedance
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL=464Ω
CL= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load cond i tion 1 Load condition 2
1999 Microchip Technology Inc. DS30235H-page 95
PIC16C62X
12.9 Timing Diagrams and Specifications
FIGURE 12-10: EXTERNAL CLOCK TIMING
TABLE 12-3: EXTERNAL CLOC K TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
1A FOSC External CLKIN Frequency
(Note 1) DC — 4 MHz XT and RC osc mode, VDD=5.0V
DC — 20 MHz HS osc mode
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode, VDD=5.0V
0.1 — 4 MHz XT osc mode
1 — 20 MHz HS osc mode
DC – 200 kHz LP osc mode
1T
OSC External CLKIN Period
(Note 1) 250 — — ns XT and RC osc mode
50 — — ns HS osc mode
5——
µs LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
50 — 1,000 ns HS osc mode
5——
µs LP osc mode
2T
CY Instruction Cycle Time (Note 1) 1.0 FOSC/4 DC µsTCYS=FOSC/4
3* TosL,
TosH External Clock in (OSC1) High or
Low Time 100* — — ns XT oscillator, TOSC L/H duty cyc le
2* — — µs LP oscillator, TOSC L/H duty cycle
20* — — ns HS oscillator, TOSC L/H duty cycle
4* TosR,
TosF External Clock in (OSC1) Rise or
Fall Time 25* — — ns XT oscillator
50* — — ns LP oscillator
15* — — ns HS oscillator
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (T CY) equals four times the input oscillator time-base period. All specified values are based on
characterization data f or that particular oscillator type under standard operating conditions with the device e xecuting code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expec ted current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all de vices .
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
133
44
2
PIC16C62X
DS30235H-page 96 1999 Microchip Technology Inc.
FIGURE 12-11: CLKOUT AND I/O TIMING
22
23
Note: All tests must be done with specified capacitance loads (Figure 12-9) 50 pF on I/O pins and CLKOUT.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new v alue
1999 Microchip Technology Inc. DS30235H-page 97
PIC16C62X
TABLE 12-4: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
#Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ (1) —
—75
—200
400 ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
11* TosH2ckH OSC1↑ to CLKOUT↑ (1) —
—75
—200
400 ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
12* TckR CLKOUT rise time (1) —
—35
—100
200 ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
13* TckF CLKOUT fall time (1) —
—35
—100
200 ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
14* TckL2ioV CLKO UT ↓ to Port out valid (1) — — 20 ns
15* TioV2ckH Port in valid bef ore CLKOUT ↑ (1) TOSC +200 ns
TOSC +400 ns —
——
—ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
16* TckH2ioI Por t in hold after CLKOUT ↑ (1) 0——ns
17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid —
—50 150
300 ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
18* TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time) 100
200 —
——
—ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
19* TioV2osH Port input valid to OSC1↑ (I/O in setup
time) 0——ns
20* TioR Port output rise time —
—10
—40
80 ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
21* TioF Port output fall time —
—10
—40
80 ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
22* Tinp RB0/INT pin high or low time 25
40 —
——
—ns
ns PIC16C62X(A)
PIC16LC62X(A)
PIC16CR62XA
PIC16LCR62XA
23 Trbp RB<7:4> change interrupt high or low
time TCY ——ns
* These parameters are characterized but not tested.
† Data in " Typ" column is at 5.0V, 25°C unless o therwise stated. These paramet ers are for desi gn guid ance onl y and are not
tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
PIC16C62X
DS30235H-page 98 1999 Microchip Technology Inc.
FIGURE 12-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 12-13: BROWN-OUT RESET TIMING
TABLE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Param eter
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse W idth (low) 2000 ——ns
-40° to +8 5 °C
31 Twdt Watchdog Timer Time-out Period
(No Prescaler) 7* 18 33* ms VDD = 5.0V, -40° to +85°C
32 Tost Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period
33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5.0V, -40° to +85°C
34 TIOZ I/O hi-impedance from MCLR low —2.0
µs
35 TBOR Brown-out Reset Pulse Width 100* — — µs3.7V
≤ VDD ≤ 4.3V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
VDD
MCLR
Internal
POR
PWRT
Timeout
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
VDD BVDD
35
1999 Microchip Technology Inc. DS30235H-page 99
PIC16C62X
FIGURE 12-14: TIMER0 CLOCK TIMING
TABLE 12-6: TIMER0 CLOCK REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* ——ns
With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
42 Tt0P T0CKI Period TCY + 40*
N— — ns N = prescale value
(1, 2, 4, ..., 256)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are fo r design guidance only and are
not tested.
41
42
40
RA4/T0CKI
TMR0
PIC16C62X
DS30235H-page 100 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 101
PIC16C62X
13.0 DEVICE CHARACTERIZATION INFORMATION
The gra phs a nd t ables provid ed i n th is se ctio n ar e for des ign guid anc e an d are not test ed. In some grap hs o r t ables,
the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only
and devices will operate properly only within the specified range.
The data presented in this secti on is a statistical summary of dat a collected on units fr om different lots over a period of
time. “Typical” represents the mean of the distribution, while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respective ly, where σ is standard deviation.
FIGURE 13-1: IDD vs. Frequency (XT Mode, VDD = 5.5V)
FIGURE 13-2: PIC16C6 22A IPD vs. VDD (WDT Disable)
0.20 1.00 2.00 4.00
Frequency (MHz)
1.20
1.00
0.8
0.6
0.4
0.2
0.00
IDD (mA)
VDD (V)
3 4 5 6
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
IPD (uA)
PIC16C62X
DS30235H-page 102 1999 Microchip Technology Inc.
FIGURE 13-3: IDD vs. VDD (XT OSC 4MHz)
FIGURE 13-4: IOI VS. VOL, VDD = 3.0V)
1.00
VDD (VOLTS)
IDD (mA)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2 2.5 3 3.5 4 4.5 5 5.5
Vol (V)
30
25
20
15
10
5
0
IOI (mA)
0 .5 1 1.5 2 2.5 3
35
40
45
50
MAX -40°C
TYP 25°C
MIN 85°C
1999 Microchip Technology Inc. DS30235H-page 103
PIC16C62X
FIGURE 13-5: IOH VS. VOH, VDD = 3.0V)
FIGURE 13-6: IOI VS. VOL, VDD = 5.5V)
VOH (V)
-10
-15
-20
-25
IOH (mA)
0 .5 1 1.5 2 2.5 3
-5
0
MAX -40°C
TYP 25°C
MIN 85°C
Vol (V)
60
50
40
30
20
10
0
IOI (mA)
0 .5 1 1.5 2 2.5 3
70
80
90
100
MAX -40°C
TYP 25°C
MIN 85°C
PIC16C62X
DS30235H-page 104 1999 Microchip Technology Inc.
FIGURE 13-7: IOH VS. VOH, VDD = 5.5V)
VOH (V)
-20
-30
-40
-50
IOH (mA)
3 3.5 4 4.5 5 5.5
-10
0
MAX -40°C
TYP 25°C
MIN 85°C
1999 Microchip Technology Inc. DS30235H-page 105
PIC16C62X
14.0 PAC KAGING INF ORMATIO N
18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
3.30 3.56 3.81
5.335.084.83.210.200.190W2Window Length .150.140.130W1Window Width 10.809.788.76.425.385.345
eB
Overall Row Spacing 0.530.470.41.021.019.016BLower Lead Width 1.521.401.27.060.055.050B1Upper Lead Width 0.300.250.20.012.010.008
c
Lead Thickness 3.813.493.18.150.138.125LTip to Seating Plane 23.3722.8622.35.920.900.880DOverall Length 7.497.377.24.295.290.285E1Ceram ic Pkg. Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.760.570.38.030.023.015A1Standoff 4.194.063.94.165.160.155A2Ceramic Package Height 4.954.644.32.195.183.170ATop to Seating Plane 2.54.100
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
1
2
D
n
W2
E1
W1
c
eB
E
p
L
A2
B
B1
A
A1
*Controlling Parameter
JEDEC Equivalent: MO-036
Drawing No. C04-010
PIC16C62X
DS30235H-page 106 1999 Microchip Technology Inc.
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.929.407.87.430.370.310eBOverall Row Spacing 0.560.460.36.022.018.014BLower Lead Width 1.781.461.14.070.058.045B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 22.9922.8022.61.905.898.890DOverall Length 6.606.356.10.260.250.240E1Molded Package Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.683.302.92.145.130.115A2Molded P ackage Thickness 4.323.943.56.170.155.140ATop to Seating Plane 2.54.100
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
1
2
D
n
E1
c
eB
β
E
α
p
A2
L
B1
B
A
A1
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
1999 Microchip Technology Inc. DS30235H-page 107
PIC16C62X
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Wi dth 0.300.270.23.012.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 11.7311.5311.33.462.454.446DOverall Length 7.597.497.39.299.295.291E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff 2.392.312.24.094.091.088
A2
Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
L
β
c
φ
h
45°
1
2
D
p
n
B
E1
E
α
A2
A1
A
*Co ntro ll ing Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
PIC16C62X
DS30235H-page 108 1999 Microchip Technology Inc.
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
φ
F oot Angle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 7.347.207.06.289.284.278DOverall Length 5.385.255.11.212.207.201
E1
Molded Package Width 8.187.857.59.322.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 2020
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
φ
α
A2
A
A1
*Contr ol li ng Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protru sions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No . C04-072
1999 Microchip Technology Inc. DS30235H-page 109
PIC16C62X
14.1 Package Marking Information
20-Lead SSOP
XXXXXXXXXX
AABBCDE
XXXXXXXXXX
XXXXXXXX
XXXXXXXX
AABBCDE
18-Lead CERDIP Windowed
18-Lead SOIC (.300")
XXXXXXXXXXXX
AABBCDE
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
AABBCDE
18-Lead PDIP
Example
-04I / 218
9951CBP
PIC16C622A
16C622
/JW
9901CBA
Example
Example
-04I / S0218
9918CDK
PIC16C622
PIC16C622A
-04I / P456
9923CBA
Example
Legend: MM...M Microchip part number information
XX...X Customer speci fic information*
AA Year code (last 2 digits of calendar year)
BB Week code (week of January 1 is week ‘01’)
C Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D Mask revision number
E Assembly code of the plant or country of origin in which
part was as sembled
Note: In the e v en t the full Mi croch ip part number canno t be ma rked on one line , it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyo nd this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
PIC16C62X
DS30235H-page 110 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 111
PIC16C62X
APPENDIX A: ENHANCEMENTS
The following are the list of enhancements over the
PIC16C5X microcontroller family:
1. Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (4K no w as opposed t o 512 bef ore) and
register file (up to 128 bytes now versus 32 bytes
before).
2. A PC high latch register (PCLATH) is added to
handle p rog ra m me mory paging. PA2, PA1 , PA0
bits are removed from STATUS register.
3. Data memory paging is slightly redefined.
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out, although they are kept for
compatibility with PIC16C5X.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized.
Registers are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delay s on po wer-up and w ake-up.
12. PORTB has weak pull-ups and interrupt on
change feature.
13. Timer0 clock input, T0CKI pin is also a port pin
(RA4/T0CKI) and has a TRIS bit.
14. FSR is made a full 8-bit register.
15. “In-circuit programming” is made possible. The
user can progr am PIC16CXX de vice s using onl y
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
16. PCON status register is added with a
Power-on-Reset (POR) status bit and a
Brown-out Reset status bit (BOD).
17. Code protection scheme is enhanced such that
portions of the program memory can be
protected, while the remainder is unprotected.
18. PORTA inputs ar e now Schmitt Trigger input s .
19. Brown-out Reset reset has been added.
20. Common RAM registers F0h-FFh implemented
in bank1.
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Ver ify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
PIC16C62X
DS30235H-page 112 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 113
PIC16C62X
INDEX
A
ADDLW Instruction .............................................................63
ADDWF Instruction.............................................................63
ANDLW Instruction .............................................................63
ANDWF Instruction.............................................................63
Architectural Overview..........................................................9
Assembler
MPASM Assembler.....................................................75
B
BCF Instruction...................................................................64
Block Diagram
TIMER0.......................................................................31
TMR0/WDT PRESCALER..........................................34
Brown-Out Detect (BOD) ....................................................50
BSF Instruction ...................................................................64
BTFSC Instruction...............................................................64
BTFSS Ins tructio n............. ..................... .............. ...............65
C
CALL Instruction .................................................................65
Clocking Scheme/Instruction Cycle ....................................12
CLRF Instru ction........... ........ ............... .............. ......... ........65
CLRW Instru ction.................. ............... ........ ............... ........66
CLRWDT Instru ction............................ ............................. ..66
CMCON Register................................................................37
Code Protection ..................................................................60
COMF Instr u c tio n............ .............. ............... ............... ........66
Comparat o r Con fig u r a tion............................ ........ ...............38
Comparator Interrupts....... .............. ............... .....................41
Comparator Module ........................ ..... .... .. .. .... .. .. ....... .. .. .. ..37
Comparator Operation................ ............... ........ ............... ..39
Comparator Reference ................................ ............... ........39
Configuration Bits................................................................46
Configuring the Voltage Reference.....................................43
Crystal Operation................................................................47
D
Data Memory Organization.................................. ........... ....14
DECF Instruction.................................................................66
DECFSZ Instruction............................................................67
Development Support .........................................................75
E
Errata ....................................................................................3
External Crystal Oscillator Circuit .......................................48
G
General purpose Register File......................... .. ......... .. .... ..14
GOTO Instruction................................................................67
I
I/O Ports............. ............... ..................... .............. ...............25
I/O Programming Considerations........................................30
ID Locations........................................................................60
Idd.....................................................................................102
INCF Instruction..................................................................67
INCFSZ Instruction .............................................................68
In-Circuit Serial Programming.............................................60
Indirect Addressing, INDF and FSR Registers ...................24
Instruction Flow/Pipelining. .................................................12
Instruction Set
ADDLW.......................................................................63
ADDWF.......................................................................63
ANDLW.......................................................................63
ANDWF.......................................................................63
BCF.............................................................................64
BSF.............................................................................64
BTFSC........................................................................ 64
BTFSS........................................................................ 65
CALL........................................................................... 65
CLRF.......................................................................... 65
CLRW......................................................................... 66
CLRWDT.................................................................... 66
COMF......................................................................... 66
DECF.......................................................................... 66
DECFSZ..................................................................... 67
GOTO......................................................................... 67
INCF........................................................................... 67
INCFSZ....................................................................... 68
IORLW........................................................................ 68
IORWF........................................................................ 68
MOVF......................................................................... 69
MOVLW...................................................................... 69
MOVWF...................................................................... 69
NOP............................................................................ 69
OPTION...................................................................... 70
RETFIE....................................................................... 70
RETLW....................................................................... 70
RETURN..................................................................... 70
RLF............................................................................. 71
RRF............................................................................ 71
SLEEP........................................................................ 71
SUBLW....................................................................... 72
SUBWF....................................................................... 72
SWAPF....................................................................... 73
TRIS ........................................................................... 73
XORLW ...................................................................... 73
XORWF...................................................................... 73
Instruction Set Summary.................................................... 61
INT Interrupt ....................................................................... 56
INTCON Register................................................................ 20
Interrupts ............................................................................ 55
Ioh............................................................................. 103, 104
IoI.............................................................................. 102, 103
IORLW Instruction. ............................................................. 68
IORWF Instruction.......... ............... ........ ............... .............. 68
K
KeeLoq Evaluation and Programming Tools ................... 78
M
MOVF Instruction................................................................ 69
MOVLW Instructio n. .............. ............... ............... ................ 69
MOVWF Instruction ............................................................ 69
MPLAB Integrated Development Environment Software.... 75
N
NOP Instruction.................................................................. 69
O
One-Time-Programmable (OTP) Devices ............................ 7
OPTION Instruction ............................................................ 70
OPTION Register................................................................ 19
Oscillato r Configurat ions......... ......... ........ ......... ................ .. 47
Oscillato r Start-up Timer (O ST)........................ ........ ........ .. 50
P
Package Marking Information........................................... 109
Packagi n g In fo rmation........ ............... ............... .............. .. 105
PCL and PCLATH............................................................... 23
PCON Register................................................................... 22
PICDEM-1 Low-Cost PICmicro Demo Board..................... 77
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 77
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 77
PICSTART Plus Entry Level Development System......... 77
PIE1 Register ..................................................................... 21
PIC16C62X
DS30235H-page 114 1999 Microchip Technology Inc.
Pinout Description..................... .. .... .. .... .. ....... .... .. .... .. ....... ..11
PIR1 Regi ster............... ............... ............... .............. ...........21
Port RB Interrupt.................................................................56
PORTA................................................................................25
PORTB................................................................................28
Power Control/Status Register (PCON)..............................51
Power-Down Mode (SLEEP )...............................................59
Power-On Reset (POR) ......................................................50
Power-up Timer (PWRT)...................................... ...............50
Prescaler.............................................................................34
PRO MA TE II Universal Programmer...............................77
Program Memory O rganization...........................................13
Q
Quick-Turnaround-Production (QTP) Devices ......................7
R
RC Oscillator.......................................................................48
Reset...................................................................................49
RETFIE Ins truction...................... ............................. ...........70
RETLW Instruction..............................................................70
RETURN Instruction............................................................70
RLF Instru ction........... ............... .............. ............... .............71
RRF Instruction............................. ............... ........ ...............71
S
SEEVAL Evaluation and Programming System...............78
Serialized Quick-Turnaround-Pr oduct ion (SQTP ) Devices...7
SLEEP In structi o n................. ..................... ..................... ....71
Softwa re Simulator (MP L AB-SIM).................... ............... ....76
Special Features of the CPU ...............................................45
Special Function Registers .................................................17
Stack...................................................................................23
Statu s Reg i ster....... ............... .............. ......... .............. .........18
SUBLW Ins truction....... ............... ............... .............. ...........72
SUBWF Instruction ..............................................................72
SWAPF Ins truction....... ............... ............... .............. ...........73
T
Timer0
TIMER0.......................................................................31
TIMER0 (TMR0) Interrupt ...........................................31
TIMER0 (TMR0) Module.............................................31
TMR0 with External Clock...........................................33
Timer1
Switching Prescaler Ass i g n men t.................... ......... ....35
Timing Diagrams and Specifications...................................95
TMR0 Interrupt....................................................................56
TRIS Instruction ................. ............... ............... ............... ....73
TRISA..................................................................................25
TRISB..................................................................................28
V
Voltage Reference Module........................... .... .. .. .... .. .. .......43
VRCON Register.................................................................43
W
Watchdog Timer (WDT)..... ......... .... .... .... ......... .... .... .... .......57
WWW, On-Line Support ........................................................3
X
XORLW Instruction .............................................................73
XORWF Instr u ction............... ........ ............... .............. .........73
1999 Microchip Technology Inc. DS30235H-page 115
PIC16C62X
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLA B are
registered trademarks of Microchip Technology Incorpo-
rated in the U.S.A. and other countri es.
Flex
ROM and
fuzzy
LAB are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
Wo rld Wide Web (WWW) site.
The we b site is used b y Mic rochi p as a mean s to mak e
files and information easily available to customers. To
vie w the site , the user must ha v e access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Ar ticles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
•Device Errata
• Job Postings
• Microchip C onsultant Program Member Li sting
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
981103
PIC16C62X
DS30235H-page 116 1999 Microchip Technology Inc.
READER RESPONSE
It is our i ntention to provide y o u w ith the bes t d ocu me ntation poss ible to ensure suc ce ssful us e of your Microchi p pro d-
uct. If you wish to provide your comments on organization, clarity, subject matter , and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
To: Technical Publications Manager
RE: Reader Response Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
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Questions:
FAX: (______) _________ - _____ ___ _
DS30235H
PIC16C62X
1999 Microchip Technology Inc. DS30235H-page 117
PIC16C62X
PIC16C62X PRODUCT IDENTIFICATION SYSTEM
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
* JW Devices are UV erasable and can be p rogrammed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a part icular device, please contact one of the following:
1. Your local Microchip sales office
2. Th e Microchip Cor porate Literature Center U.S. FA X: (480) 786-7277
3. The Microchip Worldwide Site (www.microc hip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Pattern: 3-Digit Pattern Code for QTP (blank otherwise)
Package: P=PDIP
SO = S OIC (Gull Wing, 300 mil body)
SS = SSO P (209 mil)
JW* = Windowed CERDIP
Temperature -=0°C to +70°C
Range: I = –40°C to +85°C
E = –40°C to +125°C
Frequency 04 = 200k Hz (LP osc)
Range: 04 = 4 MHz (XT and RC osc)
20 = 20 MHz (HS osc)
Device: PIC16C62X: VDD range 3.0V to 6.0V
PIC16C62XT: VDD range 3.0V to 6.0V (Tape and Reel)
PIC16C62XA: VDD range 3.0V to 5.5V
PIC16C62XAT: VDD range 3.0V to 5.5V (Tape and Reel)
PIC16LC62X: VDD range 2.5V to 6.0V
PIC16LC62XT: VDD range 2.5V to 6.0V (Tape and Reel)
PIC16LC62XA: VDD range 2.5V to 5.5V
PIC16LC62XAT: VDD range 2.5V to 5.5V (Tape and Reel)
PIC16CR620A: VDD range 2.5V to 5.5V
PIC16CR620AT: VDD range 2.5V to 5.5V (Tape and Reel)
PIC16LCR620A: VDD range 2.0V to 5.5V
PIC16LCR620AT: VDD range 2.0V to 5.5V (Tape and Reel)
Examples:
g) PIC16C621A - 04/P 301 =
Commercial temp., PDIP pack-
age, 4 MHz, normal VDD limits,
QTP pattern #301.
h) PIC16LC622- 04I/SO =
Industrial temp., SOIC pack-
age, 200kHz, extended VDD
limits.
PART NO. -XX X /XX XXX
PIC16C62X
DS30235H-page 118 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. DS30235H-page 119
PIC16C62X
NOTES:
Information cont ai ned in this publicat io n regarding device applications and the l i ke is intended for sugge st i on onl y and may be supers eded by updates. No represe nta tion or warranty is given and no liability is assumed
by Microchip Technology Incorpora ted with respect to the accuracy or us e of such informa tion, or infringe ment of patents or ot her intell ectual proper ty rights arising fr om such use or othe rwise. Use of Microc hip’s pro ducts
as critical c om ponents in life support systems is not authorized except wi th express writ ten approval by Microchip. No licenses are conveyed, impl icitly or otherwise, under any intellect ual property rights. The M i cr ochip
logo and name are registered trademarks of Mi cr ochip Technology Inc. in the U.S.A. and other countries. All rig hts reserved. All o the r tr adem arks mentioned here in are the property of their respectiv e com panies.
DS30235H-page 120 1999 Microchip Technology Inc.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 12/99 Printed on recycled paper.
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Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 7524 8
Tel: 972-818-7423 F ax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 F ax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 F a x: 248-538-2260
Los A n gel e s
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 F ax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 F ax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 F ax: 408-436-7955
AMERICAS (continued)
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Beijing
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Conv ent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Ta iw a n, R. O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Ber kshir e, Engla nd R G41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 442 0 9895 Fax: 45 4420 9910
France
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
11/15/99
WORLDWIDE SALES AND SERVICE
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication fa cilities in
Chandler and T empe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
®
8-bit MCUs, KEELOQ
®
code hoppi ng
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system f or the design and manufacture of
development systems is ISO 9001 certified.
