NBSG16MNR2 - ON Semiconductor - Datasheet.Support

September, 2008 − Rev. 18

1Publication Order Number:

NBSG16/D

NBSG16

2.5V/3.3V SiGe Differential

Receiver/Driver with

RSECL* Outputs

*Reduced Swing ECL

Description

The NBSG16 is a differential receiver/driver targeted for high

frequency applications. The device is functionally equivalent to the

EP16 and LVEP16 devices with much higher bandwidth and lower

EMI capabilities.

Inputs incorporate internal 50 W termination resistors and accept

NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL,

LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing

ECL), 400 mV.

The VBB and VMM pins are internally generated voltage supplies

available to this device only. The VBB is used as a reference voltage

for single−ended NECL or PECL inputs and the VMM pin is used as a

reference voltage for LVCMOS inputs. For all single−ended input

conditions, the unused complementary differential input is connected

to VBB or VMM as a switching reference voltage. VBB or VMM may

also rebias AC coupled inputs. When used, decouple VBB and VMM

via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.

When not used, VBB and VMM outputs should be left open.

Features

•Maximum Input Clock Frequency > 12 GHz Typical

•Maximum Input Data Rate > 12 Gb/s Typical

•120 ps Typical Propagation Delay

•40 ps Typical Rise and Fall Times

•RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V

with VEE = 0 V

•RSNECL Output with RSNECL or NECL Inputs with

Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V

•RSECL Output Level (400 mV Peak−to−Peak Output), Differential

Output Only

•50 W Internal Input Termination Resistors

•Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices

•VBB and VMM Reference Voltage Output

•Pb−Free Packages are Available

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

FCBGA−16

BA SUFFIX

CASE 489

MARKING DIAGRAMS*

QFN−16

MN SUFFIX

CASE 485G

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

ALYWG

ÇÇ

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Figure 1. BGA−16 Pinout (Top View)

VEE

DVTD

VEE VBB

VTD

NC NC VEE

VCC

VMM VEE

1234

VEE NC NC VEE

VEE VBB VMM VEE

VCC

VTD

5678

16 15 14 13

NBSG16

Exposed Pad (EP)

Figure 2. QFN−16 Pinout (Top View)

Table 1. PIN DESCRIPTION

Name I/O Description

BGA QFN

C2 1 VTD −Internal 50 W Termination Pin. See Table 2.

C1 2 D ECL, CML,

LVCMOS, LVDS,

LVTTL Input

Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.

B1 3 D ECL, CML,

LVCMOS, LVDS,

LVTTL Input

Noninverted differential input. Internal 75 kW to VEE

B2 4 VTD −Internal 50 W Termination Pin. See Table 2.

A1,D1,A4,

5,8,13,16 VEE −Negative Supply Voltage

A2,A3 6,7 NC −No Connect

B3,C3 9,12 VCC −Positive Supply Voltage

B4 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 W to

VTT = VCC − 2 V

C4 11 QRSECL Output Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V

D3 14 VMM −LVCMOS Reference Voltage Output. (VCC − VEE)/2

D2 15 VBB −ECL Reference Voltage Output

N/A −EP −The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected

to the die for improved heat transfer out of package. The exposed pad must be

attached to a heat−sinking conduit. The pad is not electrically connected to the

die but may be electrically and thermally connected to VEE on the PC board.

1. The NC pins are electrically connected to the die and MUST be left open.

2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package

bottom (see case drawing) must be attached to a heat−sinking conduit.

3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal

is applied then the device will be susceptible to self−oscillation.

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50 W

VTD

VMM

VBB

VEE

VCC

Figure 3. Logic Diagram

75 kW75 kW

36.5 KW

Table 2. INTERFACING OPTIONS

INTERFACING OPTIONS CONNECTIONS

CML Connect VTD and VTD to VCC

LVDS Connect VTD and VTD together

AC−COUPLED Bias VTD and VTD Inputs within (VIHCMR)

Common Mode Range

RSECL, PECL, NECL Standard ECL Termination Techniques

LVTTL The external voltage should be applied to the

unused complementary differential input.

Nominal voltage is 1.5 V for LVTTL.

LVCMOS VMM should be connected to the unused

complementary differential input.

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor (D, D)75 kW

Internal Input Pullup Resistor (D)36.5 kW

ESD Protection Human Body Model

Machine Model

> 2 kV

> 100 V

Moisture Sensitivity (Note 1) Pb Pkg Pb−Free Pkg

FCBGA−16

QFN−16

Level 3

Level 1

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 167

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

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Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC Positive Power Supply VEE = 0 V 3.6 V

VEE Negative Power Supply VCC = 0 V −3.6 V

VIPositive Input

Negative Input

VEE = 0 V

VCC = 0 V

VI  VCC

VI  VEE

3.6

−3.6

VINPP Differential Input Voltage |D − D| VCC − VEE w2.8 V

VCC − VEE < 2.8 V

2.8

|VCC − VEE|

Iout Output Current Continuous

Surge

IBB VBB Sink/Source 1 mA

IMM VMM Sink/Source 1 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient)

(Note 2)

0 lfpm

500 lfpm

0 lfpm

500 lfpm

FCBGA−16

QFN−16

108

41.6

35.2

°C/W

qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 2)

2S2P (Note 3)

FCBGA−16

QFN−16

4.0

°C/W

Tsol Wave Solder Pb

Pb−Free

225

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power)

3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

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Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 4)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Negative Power Supply Current 17 23 29 17 23 29 17 23 29 mA

VOH Output HIGH Voltage (Note 5) 1450 1530 1575 1525 1565 1600 1550 1590 1625 mV

VOUTPP Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV

VIH Input HIGH Voltage

(Single−Ended) (Note 6)

VTHR +

75 mV

VCC −

1.0*

VCC VTHR +

75 mV

VCC −

1.0*

VCC VTHR +

75 mV

VCC −

1.0*

VCC V

VIL Input LOW Voltage

(Single−Ended) (Note 6)

VEE VCC −

1.4*

VTHR −

75 mV

VEE VCC −

1.4*

VTHR −

75 mV

VEE VCC −

1.4*

VTHR −

75 mV

VBB PECL Output Voltage Reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mV

VIHCMR Input HIGH Voltage Common

Mode Range (Note 7)

(Differential Configuration)

1.2 2.5 1.2 2.5 1.2 2.5 V

VMM CMOS Output Voltage Reference

VCC/2

1100 1250 1400 1100 1250 1400 1100 1250 1400 mV

RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 W

IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 mA

IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

*Typicals used for testing purposes.

4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V.

5. All loading with 50 W to VCC − 2.0 V.

6. VTHR is the voltage applied to the complementary input, typically VBB or VMM.

7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

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Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 8)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Negative Power Supply Current 17 23 29 17 23 29 17 23 29 mA

VOH Output HIGH Voltage (Note 9) 2250 2330 2375 2325 2365 2400 2350 2390 2425 mV

VOUTPP Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV

VIH Input HIGH Voltage

(Single−Ended) (Note 10)

VTHR +

75 mV

VCC −

1.0*

VCC VTHR +

75 mV

VCC −

1.0*

VCC VTHR +

75 mV

VCC −

1.0*

VCC V

VIL Input LOW Voltage

(Single−Ended) (Note 10)

VEE VCC −

1.4*

VTHR −

75 mV

VEE VCC −

1.4*

VTHR −

75 mV

VEE VCC −

1.4*

VTHR −

75 mV

VBB PECL Output Voltage Reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mV

VIHCMR Input HIGH Voltage Common

Mode Range (Note 11)

(Differential Configuration)

1.2 3.3 1.2 3.3 1.2 3.3 V

VMM CMOS Output Voltage Reference

VCC/2

1500 1650 1800 1500 1650 1800 1500 1650 1800 mV

RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 W

IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 mA

IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

*Typicals used for testing purposes.

8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V.

9. All loading with 50 W to VCC − 2.0 V.

10.VTHR is the voltage applied to the complementary input, typically VBB or VMM.

11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

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Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT

VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 12)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Negative Power Supply Current 17 23 29 17 23 29 17 23 29 mA

VOH Output HIGH Voltage (Note 13) −1050 −970 −925 −975 −935 −900 −950 −910 −875 mV

VOUTPP Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV

VIH Input HIGH Voltage

(Single−Ended) (Note 14)

VTHR +

75 mV

VCC −

1.0*

VCC VTHR +

75 mV

VCC −

1.0*

VCC VTHR +

75 mV

VCC −

1.0*

VCC V

VIL Input LOW Voltage

(Single−Ended) (Note 14)

VEE VCC −

1.4*

VTHR −

75 mV

VEE VCC −

1.4*

VTHR −

75 mV

VEE VCC −

1.4*

VTHR −

75 mV

VBB NECL Output Voltage Reference −1420 −1360 −1300 −1420 −1360 −1300 −1420 −1360 −1300 mV

VIHCMR Input HIGH Voltage Common

Mode Range (Note 15)

(Differential Configuration)

VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 0.0 V

VMM CMOS Output Voltage Reference

(Note 16)

VMMT

−150

VMMT VMMT

+ 150

VMMT

−150

VMMT VMMT

+ 150

VMMT

−150

VMMT VMMT

+ 150

RTIN Internal Input Termination Resist-

45 50 55 45 50 55 45 50 55 W

IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 mA

IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

*Typicals used for testing purposes.

12.Input and output parameters vary 1:1 with VCC.

13.All loading with 50 W to VCC − 2.0 V.

14.VTHR is the voltage applied to the complementary input, typically VBB or VMM.

15.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

16.VMM typical = |VCC − VEE|/2 + VEE = VMMT

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Table 8. AC CHARACTERISTICS for FCLGA−16

VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Frequency

(See Figure 4. fmax/JITTER) (Note 17)

10.7 12 10.7 12 10.7 12 GHz

tPLH,

tPHL

Propagation Delay to

Output Differential

90 110 130 100 120 140 105 125 145 ps

tSKEW Duty Cycle Skew (Note 18) 3 15 3 15 3 15 ps

tJITTER RMS Random Clock Jitter

fin < 10 GHz

Peak−to−Peak Data Dependent Jitter

fin < 10 Gb/s

0.2

TBD

1 0.2

TBD

1 0.2

TBD

VINPP Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 19)

75 2600 75 2600 75 2600 mV

Output Rise/Fall Times @ 1 GHz Q, Q

(20% − 80%)

30 45 75 20 40 65 20 40 65 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

17.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).

18.See Figure 6. tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform.

19.VINPP(max) cannot exceed VCC − VEE

Table 9. AC CHARACTERISTICS for QFN−16

VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Frequency

(See Figure 4. fmax/JITTER) (Note 20)

10.7 12 10.7 12 10.7 12 GHz

tPLH,

tPHL

Propagation Delay to

Output Differential

90 110 130 100 120 140 95 125 145 ps

tSKEW Duty Cycle Skew (Note 21) 3 15 3 15 3 15 ps

tJITTER RMS Random Clock Jitter

fin < 10 GHz

Peak−to−Peak Data Dependent Jitter

fin < 10 Gb/s

0.2

TBD

2 0.2

TBD

2 0.2

TBD

VINPP Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 22)

75 2600 75 2600 75 2600 mV

Output Rise/Fall Times @ 1 GHz Q, Q

(20% − 80%)

20 30 50 20 30 50 20 30 50 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

20.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).

21.See Figure 6. tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform.

22.VINPP(max) cannot exceed VCC − VEE

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OUTPUT AMP

RMS JITTER

INPUT FREQUENCY (GHz)

Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.

Input Frequency (fin) at Ambient Temperature (Typical)

OUTPUT VOLTAGE AMPLITUDE (mV)

JITTEROUT ps (RMS)

700

600

500

400

300

200

100

01413121110987654321

9.5

8.5

7.5

6.5

3.5

2.5

5.5

4.5

0.5

−0.5

1.5

Figure 5. 10.709 Gb/s Diagram (3.0 V, 255C)

X = 17ps/Div Y = 70 mV/Div

Figure 6. AC Reference Measurement

tPHL

tPLH

VINPP = VIH(D) − VIL(D)

VOUTPP = VOH(Q) − VOL(Q)

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Figure 7. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

ORDERING INFORMATION

Device Package Shipping†

NBSG16BAHTBG FCBGA−16

(Pb−Free)

100 / Tape & Reel

NBSG16BA FCBGA−16 100 Units / Tray (Contact Sales Representative)

NBSG16BAR2 FCBGA−16 100 / Tape & Reel

(Contact Sales Representative)

NBSG16MN QFN−16 123 Units / Rail

NBSG16MNG QFN−16

(Pb−Free)

123 Units / Rail

NBSG16MNR2 QFN−16 3000 / Tape & Reel

NBSG16MNR2G QFN−16

(Pb−Free)

3000 / Tape & Reel

NBSG16MNHTBG QFN−16

(Pb−Free)

100 / Tape & Reel

Board Description

NBSG16BAEVB NBSG16BA Evaluation Board

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

FCBGA−16

BA SUFFIX

PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE

CASE 489−01

ISSUE O

0.20

LASER MARK FOR PIN 1

IDENTIFICATION IN

THIS AREA

0.10 Z

0.15 Z

ROTATED 90 CLOCKWISE

DETAIL K

VIEW M−M

e3 X

X0.15 YZ

0.08 Z

16 X

FEDUCIAL FOR PIN A1

IDENTIFICATION IN THIS AREA

4321

16 X

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSION b IS MEASURED AT THE MAXIMUM

SOLDER BALL DIAMETER, PARALLEL TO DATUM

PLANE Z.

4. DATUM Z (SEATING PLANE) IS DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

5. PARALLELISM MEASUREMENT SHALL EXCLUDE

ANY EFFECT OF MARK ON TOP SURFACE OF

PACKAGE.

DIM MIN MAX

MILLIMETERS

A1.40 MAX

A1 0.25 0.35

A2 1.20 REF

b0.30 0.50

D4.00 BSC

E4.00 BSC

e1.00 BSC

S0.50 BSC

−X−

−Y−

−Z−

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PACKAGE DIMENSIONS

16 PIN QFN

CASE 485G−01

ISSUE C

16X

SEATING

PLANE

0.15 C

16 13

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM

MINIMUM SPACING BETWEEN LEAD TIP

AND FLAG

ÇÇ

0.15 C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN 1

LOCATION

0.10 C

0.08 C

(A3)

16 X

16X

NOTE 5

0.10 C

0.05 C

A B

NOTE 3

16X

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D3.00 BSC

D2 1.65 1.85

E3.00 BSC

E2 1.65 1.85

e0.50 BSC

L0.30 0.50

EXPOSED PAD

0.18 TYP

ǒmm

inchesǓ

SCALE 10:1

0.50

0.02

0.575

0.022

1.50

0.059

3.25

0.128

0.30

0.012

3.25

0.128

0.30

0.012

EXPOSED PAD

*For additional information on our Pb−Free strategy and solderin

details, please download the ON Semiconductor Soldering an

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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NBSG16/D

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