DATASHEET ICM7555, ICM7556 FN2867 Rev.10.01 Mar 5, 2020 General Purpose Timers The ICM7555 and ICM7556 are CMOS RC timers providing significantly improved performance over the standard SE/NE 555/556 and 355 timers, while at the same time being direct replacements for those devices in most applications. Improved parameters include low supply current, wide operating supply voltage range, low Threshold, Trigger and Reset currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple Control Voltage for stable operation. Features Specifically, the ICM7555 and ICM7556 are stable controllers capable of producing accurate time delays or frequencies. The ICM7556 is a dual ICM7555, with the two timers operating independently of each other, sharing only V+ and GND. In the one shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. Unlike the regular bipolar SE/NE 555/556 devices, the Control Voltage terminal need not be decoupled with a capacitor. The circuits are triggered and reset on falling (negative) waveforms, and the output inverter can source or sink currents large enough to drive TTL loads, or provide minimal offsets to drive CMOS loads. * High speed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MHz Applications * Outputs have very low offsets, HIGH and LOW * Exact equivalent in most cases for SE/NE 555/556 or TLC555/556 * Low supply current - ICM7555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60A - ICM7556 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120A * Extremely low input currents . . . . . . . . . . . . . . . . . . . . . . 20pA * Guaranteed supply voltage range . . . . . . . . . . . . . . 2V to 18V * Temperature stability . . . . . . . . . . . . . 0.005%/C at +25C * Normal reset function - no crowbarring of supply during output transition * Can be used with higher impedance timing elements than regular 555/556 for longer RC time constants * Timing from microseconds through hours * Operates in both astable and monostable modes * Adjustable duty cycle * High output source/sink driver can drive TTL/CMOS * Pb-free (RoHS Compliant) * Precision timing * Pulse generation Related Literature * Sequential timing For a full list of related documents, visit our website: * Time delay generation * ICM7555 and ICM7556 device pages * Pulse width modulation * Pulse position modulation * Missing pulse detector Pin Configurations GND 1 ICM7555 (8 LD PDIP, SOIC) ICM7556 (14 LD PDIP) TOP VIEW TOP VIEW 8 VDD TRIGGER 2 7 DISCHARGE OUTPUT 3 6 THRESHOLD RESET 4 5 CONTROL VOLTAGE DISCHARGE1 1 14 VDD THRESHOLD1 2 13 DISCHARGE2 CONTROL 3 VOLTAGE1 12 THRESHOLD2 RESET1 4 OUTPUT1 5 TRIGGER1 6 GND 7 FN2867 Rev.10.01 Mar 5, 2020 11 CONTROL VOLTAGE2 10 RESET2 9 OUTPUT2 8 TRIGGER2 Page 1 of 13 ICM7555, ICM7556 Ordering Information PART NUMBER PART MARKING TEMP. RANGE (C) ICM7555CBAZ (Notes 2, 3) 7555 CBAZ 0 to +70 ICM7555CBAZ-T (Notes 1, 2, 3) 7555 CBAZ 0 to +70 ICM7555IBAZ (Notes 2, 3) 7555 IBAZ -25 to +85 ICM7555IBAZ-T (Notes 1, 2, 3) 7555 IBAZ -25 to +85 ICM7555IPAZ (Notes 2, 3) 7555 IPAZ ICM7556IPDZ (Notes 2, 3) ICM7556IPDZ TAPE AND REEL (UNITS) PACKAGE (RoHS COMPLIANT) PKG. DWG. # 8 Ld SOIC M8.15 8 Ld SOIC M8.15 8 Ld SOIC M8.15 8 Ld SOIC M8.15 -25 to +85 8 Ld PDIP E8.3 -25 to +85 14 Ld PDIP E14.3 2.5k 2.5k NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ICM7555, ICM7556. For more information on MSL, please see tech brief TB363. FN2867 Rev.10.01 Mar 5, 2020 Page 2 of 13 ICM7555, ICM7556 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18V Input Voltage Trigger, Control Voltage, Threshold, Reset (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ +0.3V to GND -0.3V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V Thermal Resistance (Typical, Notes 5, 6) JA (C/W) JC (C/W) 14 Ld PDIP Package* . . . . . . . . . . . . . . . . 115 46 8 Ld PDIP Package* . . . . . . . . . . . . . . . . . 130 69 8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . 170 67 Maximum Junction Temperature (Hermetic Package) . . . . . . . . . . . .+175C Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150C Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to +150C * Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range ICM7555C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C ICM7555I, ICM7556I . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +0.3V or less than V- -0.3V may cause destructive latch-up. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the ICM7555 and ICM7556 must be turned on first. 5. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the "case temp" location is taken at the package top center. Electrical Specifications Applies to ICM7555 and ICM7556, unless otherwise specified. TA = +25C PARAMETER Static Supply Current SYMBOL IDD TEST CONDITIONS ICM7555 ICM7556 TYP MAX UNIT VDD = 5V MIN 40 200 A VDD = 15V 60 300 A VDD = 5V 80 400 A VDD = 15V 120 600 A RA = 10k, C = 0.1F, VDD = 5V Monostable Timing Accuracy 2 % s Drift with Temperature (Note 7) VDD = 5V ppm/C VDD = 10V ppm/C VDD = 15V ppm/C Drift with Supply (Note 7) VDD = 5V to 15V 0.5 %/V Astable Timing Accuracy RA = RB = 10k, C = 0.1F, VDD = 5V 2 % Drift with Temperature (Note 7) VDD = 5V ppm/C VDD = 10V ppm/C VDD = 15V ppm/C s VDD = 5V to 15V Drift with Supply (Note 7) 0.5 %/V VTH VDD = 15V 62 67 71 % VDD Trigger Voltage VTRIG VDD = 15V 28 32 36 % VDD Trigger Current ITRIG VDD = 15V 10 nA Threshold Current ITH VDD = 15V Control Voltage VCV VDD = 15V 62 Reset Voltage VRST VDD = 2V to 15V 0.4 Threshold Voltage FN2867 Rev.10.01 Mar 5, 2020 67 10 nA 71 % VDD 1.0 V Page 3 of 13 ICM7555, ICM7556 Electrical Specifications Applies to ICM7555 and ICM7556, unless otherwise specified. (Continued) TA = +25C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Reset Current IRST VDD = 15V 10 nA Discharge Leakage IDIS VDD = 15V 10 nA Output Voltage VOL VOH Discharge Output Voltage VDD = 15V, ISINK = 20mA 0.4 1.0 V VDD = 5V, ISINK = 3.2mA 0.2 0.4 V VDD = 15V, ISOURCE = 0.8mA 14.3 14.6 V VDD = 5V, ISOURCE = 0.8mA 4.0 4.3 V VDD = 5V, ISINK = 15mA VDIS 0.2 0.4 VDD = 15V, ISINK = 15mA Supply Voltage (Note 7) Output Rise Time (Note 7) Output Fall Time (Note 7) Oscillator Frequency (Note 7) VDD V V Functional Operation 2.0 18.0 V tR RL = 10M, CL = 10pF, VDD = 5V 75 tF RL = 10M, CL = 10pF, VDD = 5V 75 ns VDD = 5V, RA = 470, RB = 270, C = 200pF 1 MHz fMAX ns NOTES: 7. These parameters are based upon characterization data and are not tested. Functional Diagram VDD 8 R THRESHOLD 6 5 CONTROL VOLTAGE 4 FLIP-FLOP RESET OUTPUT DRIVERS COMPARATOR A + - 3 7 R DISCHARGE n + TRIGGER 2 OUTPUT 1 COMPARATOR B 1 GND R NOTE: This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. FIGURE 1. FUNCTIONAL DIAGRAM TRUTH TABLE THRESHOLD VOLTAGE TRIGGER VOLTAGE Don't Care Don't Care Low Low On >2/3(V+) >1/3(V+) High Low On <2/3(V+) >1/3(V+) High Stable Stable Don't Care <1/3(V+) High High Off NOTE: RESET OUTPUT DISCHARGE SWITCH RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD. FN2867 Rev.10.01 Mar 5, 2020 Page 4 of 13 ICM7555, ICM7556 Schematic Diagram P P P R VDD P THRESHOLD N N CONTROL VOLTAGE NPN R OUTPUT P P TRIGGER R N N N N N N RESET N GND DISCHARGE R = 100k 20% (TYP) FIGURE 2. SCHEMATIC DIAGRAM Application Information General The ICM7555 and ICM7556 devices are, in most instances, direct replacements for the SE/NE 555/556 devices. However, it is possible to effect economies in the external component count using the ICM7555 and ICM7556. Because the bipolar SE/NE 555/556 devices produce large crowbar currents in the output driver, it is necessary to decouple the power supply lines with a good capacitor close to the device. The ICM7555 and ICM7556 devices produce no such transients (see Figure 3). 500 The ICM7555 and ICM7556 produce supply current spikes of only 2mA to 3mA instead of 300mA to 400mA and supply decoupling is normally not necessary. Also, in most instances, the Control Voltage decoupling capacitors are not required since the input impedance of the CMOS comparators on chip are very high. Thus, for many applications, two capacitors can be saved using an ICM7555 and three capacitors with an ICM7556. POWER SUPPLY CONSIDERATIONS Although the supply current consumed by the ICM7555 and ICM7556 devices is very low, the total system supply current can be high unless the timing components are high impedance. Therefore, use high values for R and low values for C in Figures 4, 5, and 6. GND 300 1 TRIGGER SE/NE 555 200 100 VDD 8 2 7 3 6 4 5 VDD THRESHOLD CONTROL VOLTAGE RESET 0 R ICM7555/556 0 200 400 TIME (ns) 600 800 10k DISCHARGE C OPTIONAL CAPACITOR FIGURE 4. ASTABLE OPERATION FIGURE 3. SUPPLY CURRENT TRANSIENT COMPARED WITH A STANDARD BIPOLAR 555 DURING AN OUTPUT TRANSITION FN2867 Rev.10.01 Mar 5, 2020 Page 5 of 13 ALTERNATE OUTPUT VDD OUTPUT SUPPLY CURRENT (mA) TA = +25C 400 ICM7555, ICM7556 VDD 1 VDD RA 8 2 7 OUTPUT 3 6 VDD 4 5 C tOUTPUT = -ln (1/3) RAC = 1.1RAC RA RB 1 8 TRIGGER 2 7 OUTPUT 3 RESET 4 ICM7555 DISCHARGE THRESHOLD 6 CONTROL VOLTAGE 5 OPTIONAL CAPACITOR OPTIONAL CAPACITOR C VDD 18V FIGURE 5. ALTERNATE ASTABLE CONFIGURATION FIGURE 6. MONOSTABLE OPERATION CONTROL VOLTAGE OUTPUT DRIVE CAPABILITY The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. As such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of 4.5V or more, the ICM7555 and ICM7556 will drive at least two standard TTL loads. ASTABLE OPERATION The circuit can be connected to trigger itself and free run as a multivibrator, see Figure 4. The output swings from rail-to-rail, and is a true 50% duty cycle square wave. Trip points and output swings are symmetrical. Less than a 1% frequency variation is observed over a voltage range of +5V to +15V. 1 f = -----------------1.4 RC (EQ. 1) The timer can also be connected as shown in Figure 5. In this circuit, the frequency is as shown by Equation 2: f = 1.44 ( R A + 2R B ) C The Control Voltage terminal permits the two trip voltages for the Threshold and Trigger internal comparators to be controlled. This provides the possibility of oscillation frequency modulation in the astable mode or even inhibition of oscillation, depending on the applied voltage. In the monostable mode, delay times can be changed by varying the applied voltage to the Control Voltage pin. RESET The Reset terminal is designed to have essentially the same trip voltage as the standard bipolar 555/556, i.e., 0.6V to 0.7V. At all supply voltages it represents an extremely high input impedance. The mode of operation of the Reset function is, however, much improved over the standard bipolar SE/NE 555/556 in that it controls only the internal flip-flop, which in turn controls simultaneously the state of the Output and Discharge pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices. (EQ. 2) The duty cycle is controlled by the values of RA and RB, by Equation 3: D = ( R A + R B ) ( R A + 2R B ) (EQ. 3) MONOSTABLE OPERATION In this mode of operation, the timer functions as a one-shot (see Figure 6). Initially the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of a negative Trigger pulse to pin 2, the internal flip-flop is set, which releases the short-circuit across the external capacitor and drives the Output high. The voltage across the capacitor now increases exponentially with a time constant t = RAC. When the voltage across the capacitor equals 2/3 V+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the OUTPUT to its low state. Trigger must return to a high state before the OUTPUT can return to a low state. FN2867 Rev.10.01 Mar 5, 2020 Page 6 of 13 ICM7555, ICM7556 1200 MINIMUM PULSE WIDTH (ns) SUPPLY CURRENT (ICM7555) (A) TA = +25C 1100 1000 900 800 700 600 500 VDD = 2V 400 300 200 VDD = 5V 100 VDD = 18V 200 400 180 360 160 320 280 140 TA = -20C 120 100 60 80 20 40 10 20 30 0 0 40 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) FIGURE 7. MINIMUM PULSE WIDTH REQUIRED FOR TRIGGERING FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE 100 -0.1 TA = +25C TA = -20C OUTPUT SINK CURRENT (mA) OUTPUT SOURCE CURRENT (mA) 120 40 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD) VDD = 2V VDD = 5V -10.0 VDD = 18V -1.0 -0.1 OUTPUT VOLTAGE REFERENCED TO VDD (V) 10.0 VDD = 18V 1.0 0.1 0.01 -0.01 VDD = 5V VDD = 2V 0.1 1.0 10.0 OUTPUT LOW VOLTAGE (V) FIGURE 9. OUTPUT SOURCE CURRENT vs OUTPUT VOLTAGE FIGURE 10. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE 100 100 TA = +70C VDD = 18V 10.0 OUTPUT SINK CURRENT (mA) TA = +25C OUTPUT SINK CURRENT (mA) 160 TA = +70C 0 0 -100 -10 200 TA = +25C 80 0 -1.0 240 SUPPLY CURRENT (ICM7556) (A) Typical Performance Curves VDD = 5V VDD = 2V 1.0 0.1 0.01 0.1 1.0 OUTPUT LOW VOLTAGE (V) FIGURE 11. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE FN2867 Rev.10.01 Mar 5, 2020 10.0 VDD = 18V 10.0 VDD = 5V VDD = 2V 1.0 0.1 0.01 0.1 1.0 10.0 OUTPUT LOW VOLTAGE (V) FIGURE 12. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE Page 7 of 13 ICM7555, ICM7556 (Continued) 8 100 TA = +25C 6 DISCHARGE SINK CURRENT (mA) NORMALIZED FREQUENCY DEVIATION (%) Typical Performance Curves 4 2 RA = RB = 10M C = 100pF 0 2 RA = RB = 10k C = 0.1F 4 6 8 0.1 1.0 10.0 TA = +25C 10.0 VDD = 2V 1.0 0.1 0.01 100.0 0.1 FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE MODE vs SUPPLY VOLTAGE PROPAGATION DELAY (ns) VDD = 5V 500 400 300 TA = +70C TA = +25C TA = -20C 0 0 10 20 30 40 +1.0 RA = RB = 10k C = 0.1F +0.9 +0.8 +0.7 +0.6 VDD = 5V +0.5 +0.4 VDD = 18V +0.3 +0.2 VDD = 2V +0.1 VDD = 2V 0 -0.1 0 -20 20 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD) FIGURE 15. PROPAGATION DELAY vs VOLTAGE LEVEL OF TRIGGER PULSE 80 1.0 TA = +25C 100m TA = +25C RA 10m 1k 10k 100k 1M 10M 100M (RA + 2RB) 1m 100 10 1 100n CAPACITANCE (F) CAPACITANCE (F) 60 FIGURE 16. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE MODE vs TEMPERATURE 10m 10n 1m 100 10 1 100n 1k 10k 100k 1M 10M 100M 10n 1n 1n 100p 100p 10p 1p 0.1 40 TEMPERATURE (C) 1.0 100m 10.0 FIGURE 14. DISCHARGE OUTPUT CURRENT vs DISCHARGE OUTPUT VOLTAGE NORMALIZED FREQUENCY DEVIATION (%) 600 100 1.0 DISCHARGE LOW VOLTAGE (V) SUPPLY VOLTAGE (V) 200 VDD = 5V VDD = 18V 10p 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 17. FREE RUNNING FREQUENCY vs RA, RB AND C FN2867 Rev.10.01 Mar 5, 2020 10M 1p 100n 1 10 100 1m 10m 100m 1 TIME DELAY (s) FIGURE 18. TIME DELAY IN THE MONOSTABLE MODE vs RA AND C Page 8 of 13 10 ICM7555, ICM7556 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION Mar 5, 2020 10.01 Added Related Literature section. Removed CERDIP part information. Added ESD information. Removed About Intersil Updated Disclaimer Jun 28, 2016 10.00 Converted to new datasheet template. Updated 14 Ld PDIP "Pin Configuration" on page 1 by adding "1" or "2" to pins that have same name. Updated "Thermal Information" on page 3 by removing Maximum Lead Temperature and Adding TJC values with corresponding note. Updated "Ordering Information" table on page 2 by removing obsoleted parts, adding Tape and Reel option column, adding MSL note and numbering notes accordingly. Updated POD M8.15 to most current version. POD changes are as follows: Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern FN2867 Rev.10.01 Mar 5, 2020 CHANGE Page 9 of 13 ICM7555, ICM7556 Package Outline Drawing For the most recent package outline drawing, see M8.15. M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8 0 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW "B" TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW "A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN2867 Rev.10.01 Mar 5, 2020 Page 10 of 13 ICM7555, ICM7556 For the most recent package outline drawing, see E8.3. E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP) N E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- SEATING PLANE A2 e B1 D1 B 0.210 - 0.39 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 D1 0.005 - 0.13 0.010 (0.25) M eC C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. - NOTES - A A1 MAX 0.015 L D1 MIN A E D -C- MAX A1 -ABASE PLANE MILLIMETERS MIN 5.33 - 10.16 - 4 4 5 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. eB - 0.430 L 0.115 0.150 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . N 8 2.93 8 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). FN2867 Rev.10.01 Mar 5, 2020 Page 11 of 13 ICM7555, ICM7556 For the most recent package outline drawing, see E14.3. N E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP) E1 INDEX AREA 1 2 3 N/2 INCHES -B- -AE D BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M C L eA A1 eC C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . MILLIMETERS SYMBOL MIN MAX MIN A - 0.210 - MAX A1 0.015 - 0.39 A2 0.115 0.195 2.93 4.95 B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8 5.33 - NOTES 4 4 - C 0.008 0.014 D 0.735 0.775 D1 0.005 - 0.13 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 0.300 BSC eA eB - L 0.115 N 0.204 18.66 0.430 0.150 14 0.355 19.68 - 5 5 2.54 BSC - 7.62 BSC 6 - 10.92 2.93 3.81 14 7 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN2867 Rev.10.01 Mar 5, 2020 Page 12 of 13 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES ("RENESAS") PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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