DS066 (v4.4) April 3, 2006 www.xilinx.com 1
Product Specification
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
CNT to 125 MHz
• 108 macrocells with 2,400 usable gates
• Up to 108 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 84-pin PLCC, 100-pin PQFP, 100-pin
TQFP, and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
0
XC95108 In-System
Programmable CPLD
DS066 (v4.4) April 3, 2006 05Product Specification
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Figure 1: Typical ICC vs. Frequency for XC95108
Clock Frequency (MHz)
Typical I
CC
(mA)
050
100
(180)
(250)
(170)
200
300
100
High Performance
Low Power
DS066_01_110501
XC95108 In-System Programmable CPLD
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Product Specification
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Figure 2: XC95108 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
DS066_02_110101
1
Function
Block 2
36
18
18
Function
Block 3
Macrocells
1 to 18
Macrocells
1 to 18
36
Function
Block 6
36
18
18
Function
Block 4
Macrocells
1 to 18
36
18
Function
Block 5
Macrocells
1 to 18
36
18
Fast CONNECT II Switch Matrix
XC95108 In-System Programmable CPLD
DS066 (v4.4) April 3, 2006 www.xilinx.com 3
Product Specification
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Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
Symbol Description Value Units
VCC Supply voltage relative to GND –0.5 to 7.0 V
VIN Input voltage relative to GND –0.5 to VCC + 0.5 V
VTS Voltage applied to 3-state output –0.5 to VCC + 0.5 V
TSTG Storage temperature (ambient) –65 to +150 oC
TJJunction temperature +150 oC
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Parameter Min Max Units
VCCINT Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to 70oC 4.75 5.25 V
Industrial TA = –40oC to +85oC4.5 5.5
VCCIO Supply voltage for output drivers
for 5V operation
Commercial TA = 0oC to 70oC 4.75 5.25 V
Industrial TA = –40oC to +85oC4.5 5.5
Supply voltage for output drivers for 3.3V operation 3.0 3.6
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 VCCINT + 0.5 V
VOOutput voltage 0 VCCIO V
Symbol Parameter Min Max Units
TDR Data Retention 20 - Years
NPE Program/Erase Cycles (Endurance) 10,000 - Cycles
Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 5V outputs IOH = –4.0 mA, VCC = Min 2.4 - V
Output high voltage for 3.3V outputs IOH = –3.2 mA, VCC = Min 2.4 - V
VOL Output low voltage for 5V outputs IOL = 24 mA, VCC = Min - 0.5 V
Output low voltage for 3.3V outputs IOL = 10 mA, VCC = Min - 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCC
-±10μA
IIH I/O high-Z leakage current VCC = Max
VIN = GND or VCC
-±10μA
CIN I/O capacitance VIN = GND
f = 1.0 MHz
-10pF
ICC Operating supply current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
100 (Typical) mA
XC95108 In-System Programmable CPLD
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Product Specification
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AC Characteristics
Symbol Parameter
XC95108-7 XC95108-10 XC95108-15 XC95108-20
UnitsMin Max Min Max Min Max Min Max
TPD I/O to output valid - 7.5 - 10.0 - 15.0 - 20.0 ns
TSU I/O setup time before GCK 4.5 - 6.0 - 8.0 - 10.0 - ns
THI/O hold time after GCK 0 - 0 - 0 - 0 - ns
TCO GCK to output valid - 4.5 - 6.0 - 8.0 - 10.0 ns
fCNT(1) 16-bit counter frequency 125.0 - 111.1 - 95.2 - 83.3 - MHz
fSYSTEM(2) Multiple FB internal operating
frequency
83.3 - 66.7 - 55.6 - 50.0 - MHz
TPSU I/O setup time before p-term clock
input
0.5-2.0-4.0-4.0-ns
TPH I/O hold time after p-term clock input 4.0 - 4.0 - 4.0 - 6.0 - ns
TPCO P-term clock output valid - 8.5 - 10.0 - 12.0 - 16.0 ns
TOE GTS to output valid - 5.5 - 6.0 - 11.0 - 16.0 ns
TOD GTS to output disable - 5.5 - 6.0 - 11.0 - 16.0 ns
TPOE Product term OE to output enabled - 9.5 - 10.0 - 14.0 - 18.0 ns
TPOD Product term OE to output disabled - 9.5 - 10.0 - 14.0 - 18.0 ns
TWLH GCK pulse width (High or Low) 4.0 - 4.5 - 5.5 - 5.5 - ns
TAPRPW Asynchronous preset/reset pulse
width (High or Low)
7.0-7.5-8.0-8.0-ns
Notes:
1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
Figure 3: AC Load Circuit
Device Output
Output Type VTEST
5.0V
3.3V
VTEST
R1
160Ω
260Ω
R1
R2CL
R2
120Ω
360Ω
CL
35 pF
35 pF
DS067_03_110101
VCCIO
5.0V
3.3V
XC95108 In-System Programmable CPLD
DS066 (v4.4) April 3, 2006 www.xilinx.com 5
Product Specification
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Internal Timing Parameters
Symbol Parameter
XC95108-7 XC95108-10 XC95108-15 XC95108-20
UnitsMinMaxMinMaxMinMaxMinMax
Buffer Delays
TIN Input buffer delay - 2.5 - 3.5 - 4.5 - 6.5 ns
TGCK GCK buffer delay - 1.5 - 2.5 - 3.0 - 3.0 ns
TGSR GSR buffer delay - 4.5 - 6.0 - 7.5 - 9.5 ns
TGTS GTS buffer delay - 5.5 - 6.0 - 11.0 - 16.0 ns
TOUT Output buffer delay - 2.5 - 3.0 - 4.5 - 6.5 ns
TEN Output buffer enable/disable delay - 0 - 0 - 0 - 0 ns
Product Term Control Delays
TPTCK Product term clock delay - 3.0 - 3.0 - 2.5 - 2.5 ns
TPTSR Product term set/reset delay - 2.0 - 2.5 - 3.0 - 3.0 ns
TPTTS Product term 3-state delay - 4.5 - 3.5 - 5.0 - 5.0 ns
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay - 0.5 - 1.0 - 3.0 - 4.0 ns
TSUI Register setup time 1.5 - 2.5 - 3.5 - 3.5 - ns
THI Register hold time 3.0 - 3.5 - 4.5 - 6.5 - ns
TCOI Register clock to output valid time - 0.5 - 0.5 - 0.5 - 0.5 ns
TAOI Register async. S/R to output delay - 6.5 - 7.0 - 8.0 - 8.0 ns
TRAI Register async. S/R recover before clock 7.5 - 10.0 - 10.0 - 10.0 - ns
TLOGI Internal logic delay - 2.0 - 2.5 - 3.0 - 3.0 ns
TLOGILP Internal low power logic delay - 10.0 - 11.0 - 11.5 - 11.5 ns
Feedback Delays
TFFastCONNECT feedback delay - 8.0 - 9.5 - 11.0 - 13.0 ns
TLF Function block local feedback delay - 4.0 - 3.5 - 3.5 - 5.0 ns
Time Adders
TPTA(1) Incremental product term allocator delay - 1.0 - 1.0 - 1.0 - 1.5 ns
TSLEW Slew-rate limited delay - 4.0 - 4.5 - 5.0 - 5.5 ns
Notes:
1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
XC95108 In-System Programmable CPLD
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Product Specification
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XC95108 I/O Pins
Function
Block
Macro-
cell PC84 PQ100 TQ100 PQ160
BScan
Order
Function
Block
Macro-
cell PC84 PQ100 TQ100 PQ160
BScan
Order
1 1 –– –25321 3 1 –– –45213
1 2 1 15 13 21 318 3 2 14 31 29 47 210
1 3 2 16 14 22 315 3 3 15 32 30 49 207
1 4 –211929312 3 4 –363457204
1 5 3 17 15 23 309 3 5 17 34 32 54 201
1 6 4 18 16 24 306 3 6 18 35 33 56 198
1 7 –– –27303 3 7 –– –50195
1 8 5 19 17 26 300 3 8 19 37 35 58 192
1 9 6 20 18 28 297 3 9 20 38 36 59 189
1 10 – 26 24 36 294 3 10 – 45 43 69 186
1 11 7 22 20 30 291 3 11 21 39 37 60 183
1129
[1] 24[1] 22[1] 33[1] 288[1] 3 12 23 41 39 62 180
1 13 – – – 34 285 3 13 – – – 52 177
11410
[1] 25[1] 23[1] 35[1] 282[1] 3 14 24 42 40 63 174
1 1511272537279 3 152543 4164171
11612
[1] 29[1] 27[1] 42[1] 276[1] 3 16 26 44 42 68 168
1 17 1330 28 44273 3 17 3151 49 77165
1 18 – – – 43 270 3 18 – – – 74 162
2 1 – – – 158 267 4 1 – – – 123 159
2 2 71 98 96 154 264 4 2 57 83 81 134 156
2 3 72 99 97 156 261 4 3 58 84 82 135 153
2 4 – 4 2 4 258 4 4 – 82 80 133 150
2574
[1] 1[1] 99[1] 159[1] 255[1] 4 5 61 87 85 138 147
2 6 75 3 1 2 252 4 6 62 88 86 139 144
2 7 – – – 9 249 4 7 – – – 128 141
2876
[1] 5[1] 3[1] 6[1] 246[1] 4 8 63 89 87 140 138
2977
[1] 6[1] 4[1] 8[1] 243[1] 4 9 65 91 89 142 135
2 10 – 9 7 12 240 4 10 – – – 147 132
2 11 79 8 6 11 237 4 11 66 92 90 143 129
2 12 80 10 8 13 234 4 12 67 93 91 144 126
2 13 – – – 14 231 4 13 – – – 153 123
2 14 81 11 9 15 228 4 14 68 95 93 146 120
2 15 8212 10 17225 4 15 6996 94148117
2 16 83 13 11 18 222 4 16 – 94 92 145 114
2 17 8414 12 19219 4 17 7097 95152111
2 18 – – – 16 216 4 18 – – – 155 108
Notes:
1. Global control pin.
XC95108 In-System Programmable CPLD
DS066 (v4.4) April 3, 2006 www.xilinx.com 7
Product Specification
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XC95108 Global, JTAG, and Power Pins
5 1 –– –76105 6 1 –– –9151
5 2 32 52 50 79 102 6 2 45 67 65 103 48
5 3 33 54 52 82 99 6 3 46 68 66 104 45
5 4 – 48 46 72 96 6 4 – 75 73 116 42
5 5 34 55 53 86 93 6 5 47 69 67 106 39
5 6 35 56 54 88 90 6 6 48 70 68 108 36
5 7 – – – 78 87 6 7 – – – 105 33
5 8 36 57 55 90 84 6 8 50 72 70 111 30
5 9 37 58 56 92 81 6 9 51 73 71 113 27
5 10 – – – 84 78 6 10 – – – 107 24
5 11 39 60 58 95 75 6 11 52 74 72 115 21
5 12 40 62 60 97 72 6 12 53 76 74 117 18
5 13 – – – 87 69 6 13 – – – 112 15
5 14 41 63 61 98 66 6 14 54 78 76 122 12
5 15 43 65 63 101 63 6 15 55 79 77 124 9
5 16 – 61 59 96 60 6 16 – 81 79 129 6
5 17 44 66 64 102 57 6 17 56 80 78 126 3
5 18 – – – 89 54 6 18 – – – 114 0
XC95108 I/O Pins (Continued)
Function
Block
Macro-
cell PC84 PQ100 TQ100 PQ160
BScan
Order
Function
Block
Macro-
cell PC84 PQ100 TQ100 PQ160
BScan
Order
Pin Type PC84 PQ100 TQ100 PQ160
I/O/GCK1 9 24 22 33
I/O/GCK2 10 25 23 35
I/O/GCK3 12 29 27 42
I/O/GTS176536
I/O/GTS277648
I/O/GSR 74 1 99 159
TCK30504875
TDI28474571
TDO 59 85 83 136
TMS29494773
VCCINT 5V 38,73,78 7,59,100 5,57,98 10,46,94,157
VCCIO 3.3V/5V 22,64 28,40,53,90 26,38,51,88 1,41,61,81,121,141
GND 8,16,27,42,49,60 2,23,33,46,64,71,77,86 100,21,31,44,62,69,75,84 20,31,40,51,70,80,99
GND – – – 100,110,120,127,137
GND – – – 160
No connects – – – 3,5,7,32,38,39,48,53,55,6
5,66,67,83,85,93,109,
118,119,125,130,131,
132,149,150,151
XC95108 In-System Programmable CPLD
8www.xilinx.com DS066 (v4.4) April 3, 2006
Product Specification
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Device Part Marking and Ordering Combination Information
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range(1)
XC95108-7PC84C 7.5 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) C
XC95108-7PCG84C 7.5 ns PGC84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC95108-7PQ100C 7.5 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C
XC95108-7PQG100C 7.5 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-7TQ100C 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C
XC95108-7TQG100C 7.5 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C
XC95108-7PQ160C 7.5 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) C
XC95108-7PQG160C 7.5 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-7PC84I 7.5 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) I
XC95108-7PCG84I 7.5 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC95108-7PQ100I 7.5 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) I
XC95108-7PQG100I 7.5 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC95108-7TQ100I 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I
XC95108-7TQG100I 7.5 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I
XC95108-7PQ160I 7.5 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) I
XC95108-7PQG160I 7.5 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC95108-10PC84C 10 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) C
XC95108-10PCG84C 10 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC95108-10PQ100C 10 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C
XC95108-10PQG100C 10 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-10TQ100C 10 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C
XC95108-10TQG100C 10 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C
XC95108-10PQ160C 10 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) C
XC95108-10PQG160C 10 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-10PC84I 10 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) I
XC95108-10PCG84I 10 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC95108-10PQ100I 10 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) I
XC95108-10PQG100I 10 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC95108-10TQ100I 10 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I
XC95108-10TQG100I 10 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I
XC95108-10PQ160I 10 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) I
XC95108-10PQG160I 10 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC95108-15PC84C 15 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) C
XC95xxx
TQ144
7C
Device Type
Package
Speed
Operating Range
This line not
related to device
part number
Sample package with part marking.
R
1
XC95108 In-System Programmable CPLD
DS066 (v4.4) April 3, 2006 www.xilinx.com 9
Product Specification
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XC95108-15PCG84C 15 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC95108-15PQ100C 15 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C
XC95108-15PQG100C 15 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-15TQ100C 15 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C
XC95108-15TQG100C 15 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C
XC95108-15PQ160C 15 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) C
XC95108-15PQG160C 15 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-15PC84I 15 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) I
XC95108-15PCG84I 15 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC95108-15PQ100I 15 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) I
XC95108-15PQG100I 15 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC95108-15TQ100I 15 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I
XC95108-15TQG100I 15 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I
XC95108-15PQ160I 15 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) I
XC95108-15PQG160I 15 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC95108-20PC84C 20 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) C
XC95108-20PCG84C 20 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC95108-20PQ100C 20 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C
XC95108-20PQG100C 20 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-20TQ100C 20 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C
XC95108-20TQG100C 20 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C
XC95108-20PQ160C 20 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) C
XC95108-20PQG160C 20 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC95108-20PC84I 20 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) I
XC95108-20PCG84I 20 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC95108-20PQ100I 20 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) I
XC95108-20PQG100I 20 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC95108-20TQ100I 20 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I
XC95108-20TQG100I 20 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I
XC95108-20PQ160I 20 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) I
XC95108-20PQG160I 20 ns PQG160 160-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
Notes:
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range(1)
XC95108 In-System Programmable CPLD
10 www.xilinx.com DS066 (v4.4) April 3, 2006
Product Specification
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Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
XC9500 Data Sheets and Application Notes
Device Packaging
Online Store
Revision History
The following table shows the revision history for this document.
Date Version Revision
12/04/98 3.0 Update AC characteristics and internal parameters.
06/18/03 4.0 Updated format.
08/21/03 4.1 Updated Package Device Marking Pin 1 orientation.
03/01/04 4.2 Updated table on page 8 for PQ160 pins.
04/15/05 4.3 Added asynchronous preset/reset pulse width specification (TAPRPW).
04/03/06 4.4 Added Warranty Disclaimer. Added Pb-Free package ordering information.
