MB89P475P-SH-201 - Fujitsu Semiconductor

Revision 2.0

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89470 Series

MB89475/P475/PV470

■DESCRIPTION

The MB 89470 se ries has b een develope d as a gene ral-purpos e version of the F2MC*-8L fa mily co nsistin g of

proprietary 8-bit, single-chip microcontrollers.

In additio n to a compact instruc tion set, the microc ontroller con tains a variety of perip heral functions suc h as

21-bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, external interrupt 1

(edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset.

The MB89470 series is designed suitable for home appliance as well as in a wide range of applications for

consumer product.

*: F2MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Package used

QFP package and SH-DIP package for MB89P475, MB89475

MQFP package for MB89PV470

• High-s pee d operati ng ca pabi li ty at low volta ge

• Minimum execution time: 0.32 µs/12.5MHz (Continued)

■PACKAGE

(MQP-48C-P01)

48-pin Ceramic MQFP

(FPT-48P-M05)

48-pin Plastic QFP

(DIP-48P-M01)

48-pin Plastic SH-DIP

MB89470 Series

(Continued)

•F2MC-8L family CPU core

•Six tim ers

PWC timer (also usable as a interval timer)

PWM ti mer

8/16-bit timer/counter x 2

21-bit timebase timer

Watch prescaler

•Buzzer

7 frequency types are selectable by software

•External interrupts

Edge detection (Selectable edge) : 4 channels

Low-level interrupt (Wake-up function) : 5 channels

•A/D converter (8 channels)

10-bit successive approximation type

•UART/SIO

Synchronous/asynchronous data transfer capable

•Low-powe r co nsumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

Subclock mode (for dual clock product)

Watch mode (for dual clock product)

•W atch dog timer reset

•I/O ports: max. 39 channels

Multiplication and division instructions

16-bit arithmetic operations

Test and branc h instr uc tio ns

Bit manipulation instructions, etc.

Instruction set optimized for controllers

MB89470 Series

■PRODUCT LINEUP

Note : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. (Continued)

MB89475 MB89P475 MB89PV470

Classification Mass production products

(mask ROM product) OTP

(read protection) Piggy-back

ROM size 16K x 8-bit (internal ROM) 16K x 8-bit (internal PROM, can

be written to by FLASH pro-

grammer)

32K x 8-bit (external ROM)

RAM size 512 x 8 bits 1K × 8 bits

CPU functions Number of instructions: : 136

Instruction bit length: : 8 bits

Instruction length: : 1 to 3 bytes

Data bit length: : 1, 8, 16 bits

Minimum execution time: : 0.32 µs/12.5 MHz

Minimum interru pt proc es si ng tim e: : 2.88 µs/12.5 MHz

Ports Output-only ports (N-channel open drain) : 7 pins

Input-only ports : 3 pins (1 pin in product with dual

clock)

I/O ports (CMOS) : 29 pins

Total : 39 pins

21-Bit Tim e-ba se

timer Interrupt period (0.82ms, 3.3 ms, 26.2 ms, 419.4 ms) at 10 MHz

Interrupt period (0.66ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz

Watchdog timer Reset period (209.7 ms to 419.4 ms) at 10 MHz

Reset period (167.8 ms to 335.5 ms) at 12.5 MHz

Pulse width count

timer

2 channels

8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst,

external)

8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst,

external)

8-bit pulse width measurement operation (supports continuous measurement, H width, L width,

rising edge to rising edge, falling edge to falling edge measurement and both edge

measurement)

PWM timer 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst,

external)

8-bit resolution PWM operation

8/16-Bit timer/counter

1, 2

Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its

own independent operating clock cycle), or as one 16-bit timer/counter

In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered)

and square wave output capable

8/16-Bit timer/counter

3, 4

Can be operated either as a 2-channel 8-bit timer/counter (Timer 3 and Timer 4, each with its

own independent operating clock cycle), or as one 16-bit timer/counter

In Timer 3 or 16-bit timer/counter operation, event counter operation (external clock-triggered)

and square wave output capable

External interrupt 4 independent channels (selectable edge, interrupt vector, request flag)

5 channels (low lev el interrup t)

A/D converter 10-bit resolu tion × 8 channels

A/D conversion function (conversion time: 60 tinst )

Supports repeated activation by internal clock.

UART/SIO Synchronous/asynchronous data transfer capable

(Max. baud rate: 78.125 Kbps at 10 MHz)

(7 and 8 bits with parity bit ; 8 and 9 bits without parity bit)

Part number

Parameter

Part number

Parameter

MB89470 Series

(Continued)

■PACKAGE AND CORRESPONDING PRODUCTS

O : Availabe

X : Not available

■DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

•The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

•For the MB89PV470, add the current consumed by the EPROM mounted in the piggy-back socket.

•When o per at ing a t low spe ed, th e cur ren t c on su med b y th e one -time P R OM pr od uc t is g re ater tha n that for

the mask ROM product. However, the current consumption are roughly the same in sleep or stop mode.

•For more information, see “■ Electrical Characteristics.”

3. Oscil lation stabilizati on time after power-on reset

•For MB89PV470, there is no power-on stabilization time after power-on reset

•For MB89P475, there is power-on stabilization time after power-on reset

•For MB89475, the power-on stabilization time can be select.

•For more information, refer to “■ Mask Opt ion”.

MB89475 MB89P475 MB89PV470

Buzzer output 7 frequency types (FCH/212, FCH/211, FCH/210, FCH/29, FCL/25, FCL/24, FCL/23, ) are selectable by

software.

Standby mode Sleep mode, stop mode, subclock mode(dual clock product) and watch mode(dual clock

product)

Process CMOS

Operating Voltage 2.2V ~ 5.5V 3.5V ~ 5.5V 2.7V ~ 5.5V

Device

Package MB89475 MB89P475 MB89PV470

DIP-48P-M01 O O X

FPT-48P-M05 OOX

MQP-48C-P01 XXO

Part number

Parameter

Part number

Parameter

MB89470 Series

■PIN ASSIGNMENT

VSS

C(see note)

P40/X0A

P41/X1A

P17/TO2

P16/EC2

P15/TO1

P14/EC1

P13/INT13

P12/INT12

P11/INT11

P10/INT10

P07/AN7

P06/AN6

P05/AN5

P04/AN4

P03/AN3

P02/AN2

P01/AN1

P00/AN0

AVss

AVcc

P54/INT24

P53/INT23

MODE

P42

RST

P20/SCK1

P21/SO1

P22/SI1

P23/PWC

P24/PWM

P25/SI2

VCC

P26/SO2

P27/SCK2

P30/BUZ *

P31 *

P32 *

P33 *

P34 *

P35 *

P36 *

P50/INT20

P51/INT21

P52/INT22

(DIP-48P-M01)

Note : For pin no. 2, connect this pin to an external 0.1µF

capacitor to ground (for MB89P475 only). For

MB89PV470 and MB89475, this pin should be left

unconnected.

* High current drive type

MB89470 Series

Note : For pin no. 20, connec t this pin to an external 0.1µF

capacitor to ground (for MB89P475only). For

MB89PV470 and MB89475, this pin should be left

unconnected.

* High current drive type

* P33

* P32

* P31

* P30/BUZ

P27/SCK2

P26/SO2

VCC

P25/SI2

P24/PWM

P23/PWC

P22/SI1

P21/SO1

P20/SCK1

RST

P42

MODE

VSS

C(see note)

P40/X0A

P41/X1A

P17/TO2

P16/EC2

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

P07/AN7

P10/INT10

P11/INT11

P12/INT12

P13/INT13

P14/EC1

P15/TO1

P34 *

P35 *

P36 *

P50/INT20

P51/INT21

P52/INT22

P53/INT23

P54/INT24

AVcc

AVss

P00/AN0

P01/AN1

(TOP VIEW)

(FPT-48P-M05)

MB89470 Series

*1: Package upper-side pin assignment ( MB89PV 470 only)

N.C.: As connected internally, do not use.

Pin No. Pin Symbol Pin No. Pin Symbol Pin No. Pin Symbol Pin No. Pin Symbol

49 Vpp 57 N.C. 65 O4 73 OE

50 A12 58 A2 66 O5 74 N.C.

51 A7 59 A1 67 O6 75 A11

52 A6 60 A0 68 O7 76 A9

53 A5 61 O1 69 O8 77 A8

54 A4 62 O2 70 CE 78 A13

55 A3 63 O3 71 A10 79 A14

56 N.C. 64 Vss 72 N.C. 80 Vcc

Note : Pin no. 20 should be left unconnected.

* High current drive type

* P33

* P32

* P31

* P30/BUZ

P27/SCK2

P26/SO2

VCC

P25/SI2

P24/PWM

P23/PWC

P22/SI1

P21/SO1

P20/SCK1

RST

P42

MODE

VSS

C(see note)

P40/X0A

P41/X1A

P17/TO2

P16/EC2

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

P07/AN7

P10/INT10

P11/INT11

P12/INT12

P13/INT13

P14/EC1

P15/TO1

P34 *

P35 *

P36 *

P50/INT20

P51/INT21

P52/INT22

P53/INT23

P54/INT24

AVcc

AVss

P00/AN0

P01/AN1

(TOP VIEW)

(MQP-48C-P01)

MB89470 Series

■PIN DESCRIPTION

(Continued)

Pin no. Pin name I/O

circuit Function

QFP/MQFP*2SDIP*1

17 47 X0 AConnect ion pins for a crystal or other oscillator.

An external clock can be connected to X0. In this case , leave X1 open.

18 48 X1

16 46 MODE B Input pins for setting the memory access mode.

Connect directly to VSS.

14 44 RST C

Reset I/O pin. The pin is a N-ch open-drain type with pull-up resistor and a hysteresis

input. The pin outputs a “L” level when an internal reset request is present. Inputting

an “L” level initializ es internal circuits.

38 - 31 20 - 13 P00/AN0 -

P07/AN7 DGeneral-purpose I/O port.

The pins are shared with the analog inputs for the A/D converter.

30 - 27 12 - 9 P10/INT10 -

P13/INT13 EGeneral-purpose I/O port.

A hysteresis input for INT10~13.

The pin is shared with an external interrupt 1 input.

26 8 P14/EC1 E General-purpose I/O port.

A hysteresis input for EC1.

The pin is shared with the 8/16 bit timer 1 input.

25 7 P15/TO1 F General-purpose I/O port.

The pin is shared with the output of 8/16-bit timer 1.

24 6 P16/EC2 E General-purpose I/O port.

A hysteresis input for EC2.

The pin is shared with the 8/16 bit timer 2 input.

23 5 P17/TO2 F General-purpose I/O port.

The pin is shared with the output of 8/16-bit timer 2.

13 43 P20/SCK1 E General-purpose I/O port.

A hysteresis input for SCK1.

The pin is shared with the clock I/O of UART/SIO 1.

12 42 P21/SO1 F General-purpose I/O port.

The pin is shared with the serial data output of UART/SIO 1.

11 41 P22/SI1 E General-purpose I/O port.

A hysteresis input for SI1.

The pin is shared with the serial data input of UART/SIO 1.

10 40 P23/PWC E General-purpose I/O port.

A hysteresis input for PWC.

This pin is shared with PWC input.

9 39 P24/PWM F General-purpose input port.

This pin is shared with PWM output.

8 38 P25/SI2 E General-purpose I/O port.

A hysteresis input for SI2.

The pin is shared with the serial data input of UART/SIO 2.

6 36P26/SO2F

General-purpose I/O port.

The pin is shared with the serial data output of UART/SIO 2.

5 35 P27/SCK2 E General-purpose I/O port.

A hysteresis input for SCK2.

The pin is shared with the clock I/O of UART/SIO 2.

MB89470 Series

(Continued)

*1: DIP-48P-M01

*2: FPT-48P-M05 / MQP-48C-P01

*3: When MB89475 or MB89PV470 is used, this pin will become a N.C. pin without internal connection.

When MB89P475 is used, connect this pin to an external 0.1uF capacitor to ground.

Pin no. Pin name I/O

circuit Function

QFP/MQFP*2SDIP*1

4 34 P30/BUZ G N-channel open-drain output.

The pin is shared with buzzer output.

3 - 1, 48 - 46 33 - 28 P31 - P36 G N-channel open-drain output.

21 4 P40/X0A H G ener al-purpose input port. (single clock system )

AConnection pins for a crystal or other oscillator. (dual clock system)

An external clock can be connected to X0A. In this case, leave X1A open.

22 3 P41/X1A H G ener al-purpose input port. (single clock system )

AConnection pins for a crystal or other oscillator. (dual clock system)

An external clock can be connected to X0A. In this case, leave X1A open.

15 45 P42 H General-purpose input port.

45 - 41 27 - 23 P50/INT20 -

P54/INT24 EGeneral-purpose I/O port.

A hysteresis input for INT20~INT24.

The pin is shared with an external inte rrupt 2 input.

20 2 C —Capacitor connection pin *3

737V

CC —Power supply pin (+5V).

19 1 VSS —Power supply pin (GND).

40 22 AVCC —A/D converter power supply pin.

39 21 AVSS —A/D converter power supply pin.

Use at the same voltage level as VSS.

MB89470 Series

• External EPROM Socket (MB89PV470 only)

*1: MQP-48C-P01

Pin Number Pin

Name I/O Function

MQFP*1

49 Vpp O“H” level output pin

A12

O Address output pins.

O3 I Data input pins.

64 VSS O Power supply pin (GND).

I Data input pins.

70 CE O Chip enable pin for the ROM. Outputs “H” in st andby mode.

71 A10 O Address output pin.

72 OE O Output enable pin for the ROM. A lways outpu ts “L”.

A11

A13

A14

O Address output pins.

80 VCC O Power supply pin for the EPROM.

N.C. —Internally connected pins. Always leave open.

MB89470 Series

■I/O CIRCUIT TYPE

(Continued)

Circuit

Class Circuit Remarks

A•Main and sub-clock circuits

•Hysteresis input

•The pull-down resistor is

approx. 50kΩ.

(No pull-down resistor in

MB89P475)

C•The pull-up resistance (P-

channel) is approx. 50 kΩ.

•Hysteresis input

•CMOS output

•CMOS input

•Selectable pull-up resistor

Approx. 50 kΩ

•CMOS output

•CMOS input

•Selectable pull-up resistor

Approx. 50 kΩ

X1 (X1A)

X0 (X0 A )

Nch Pch

Pch

Nch

Stop mode control signal

Pch

Nch

Pch

Nch

Rpull-up

resistor register

ADIN

Pch

Nch

port

resources

pull-up

resistor register

MB89470 Series

(Continued)

•CMOS output

•CMOS input

•Selectable pull-up resistor

Approx. 50 kΩ

G•N-channel open-drain output

•Selectable pull-up resistor

Approx. 50 kΩ

H•CMOS input

Pch

Nch

Rpull-up

resistor register

Pch

Nch

Rpull-up

resistor register

port

MB89470 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other t han medium- to hi gh-voltage pi ns or if highe r than the voltag e which show s on “1. Absolute Maximum

Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prev ent the analo g power sup ply (A VCC) a nd ana log in put from ex ceedi ng the digit al powe r

supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = VCC and AVSS = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is

therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations

(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

MB89470 Series

■PROGRAMMING OTPROM IN MB89P475 WITH SERIAL PROGRAMMER

1. Programming the OTPROM with serial progr ammer

•All OTP products can be programmed with serial programmer

2. Programming the OTPROM

•To program the OTPROM using EPROM programmer AF200 (manufacturer: Yokogawa Digital Computer

Corp.).Inquiry : Yokogawa Digital Computer Corp. : TEL (81)-42-333-6224

•To program the OTPROM using FUJITSU MCU programmer MB91919-001.

Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770

FAX (65)-28102 20

3. Programming Adaptor for OTPROM

•To progra m the OTPRO M using EP ROM prog ramme r AF200, use the progr amming ada pter (man ufactu rer:

Sun Hayato Co., Ltd.) listed below.

Inquiry : Sun Hayato Co., Ltd : TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

•To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter

listed below.

Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770

FAX (65)-2810220

4. OTPROM Content Protection

For product with OTPROM content protection feature (MB89P475-102, MB89P475-202), OTPROM content can

be read using serial programmer if the OTPROM content protection mechanism is not activated.

One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM

content. If the protection code "00H" is written in this address (FFFCH), the OTPROM content cannot be read by

any serial programmer.

Note: The program written into the OTPROM cannot be verified once the OTPROM protection code is written

("00H" in FFFCH). It is advised to write the OTPROM protection code at last.

5. Programming Yiel d

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer , due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

Package Compatible socker adaptor

DIP-48P-M01 N/A

FPT-48P-M05 T.B.D.

Package Compatible socker adaptor

DIP-48P-M01 T.B.D.

FPT-48P-M05 T.B.D.

MB89470 Series

■PROGRAMMING OTPROM IN MB89P475 WITH GENERAL PURPOSE EPROM PRO-

GRAMMER

1. Programming OTPROM with general purpose EPROM programmmer

•Only products without protection feature (i.e. MB89P475-101 and MB89P475-201) can be programmed with

general purpose EPROM programmer. Product with protection feature (i.e. MB89P475-102 and MB89P475-

202) cannot be programmed with general purpose programmer.

2. ROM Writer Adapters and Recommended ROM Writers

•The following shows ROM writer adapters and recommended ROM writers.

•Contact information

Sun Hayato Co., Ltd.: Phone 03-3986-0403

Minato electronics Co., Ltd.: Phone 045-591-5611

3. W riting data to the EPROM

(1) Set the EPROM writer for the CU50-OTP (device code: cdB6DC).

(2) Load the program data to the EPROM writer.

(3) Write data using the EPROM writer .

4. Programming Yiel d

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer , due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

Package name

Applicable adapter model Recommended writer maker and writer

San Hayato Co., Ltd. Minato electronics Co., Ltd.

MODEL1890A

DIP-64P-M01 N/A N/A

FPT-48P-M05 T.B.D Under evaluation

MB89470 Series

■PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

To prog ram to the PROM usi ng an EPROM program mer, u se the socket adap ter (manufactur er: Sun Hayato

Co., Ltd.) listed below.

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403

3. Memory Space

Memory space in each mode is diagrammed below.

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256.

(2) Load program data into the EPROM programmer at 0000H to 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

Package Adapter socket part number

LCC-32 (Squa re) RO M-32L C-28DP - S

Address

Normal operating mode Corresponding addres ses on the EPR OM progra mm er

0000H

7FFFH

0000H

0080H

0880H

8000H

FFFFH

I/O

RAM

Not available

PROM

32KB EPROM

32KB

MB89470 Series

■ Block Diagram

Oscillator

Clock controller

1K Byte RAM / 512 By te RAM

F2MC-8L

CPU

16K Byte ROM

Other pins

MODE, VCC, VSS, C *2

Internal data bus

21-bit Time-base

timer

Reset circuit

(Watchdog timer)

RST

CMOS I/O port 2

CMOS I/O Port 0

10-bit A/D converter

P00/AN0

to P07/AN7

AVCC

AVSS

CMOS I/O port 1

Buzzer

N-ch open-drain output port 3

4P10/INT10 to P13/INT13

P14/EC1

P17/TO2

P16/EC2

P15/TO1

6P31*1 to P36 *1

P30/BUZ *1

UART/SIO 1 P22/SI1

P21/SO1

P20/SCK1

UART/SIO 2 P27/SCK2

P26/SO2

P25/SI2

8-bit PWM P24/PWM

P23/PWC

*1 : High Current Pins

*2 : Unconnected pin for MB89PV470 and MB89475

Sub-clock Oscillator

Watch Prescaler

P40/X0A

P41/X1A

CMOS Input port 4

P42

8/16-bit Timer 1,2

8/16-bit Timer 3,4

8-bit PWC

External interrupt 2

(Level)

CMOS I/O port 5

P50/INT20 to

P54/INT24 5

External interrupt 1

(Edge)

MB89470 Series

■CPU CORE

1. Memory Space

The microcontrollers of the MB89470 series offer a memory space of 64 Kbytes for storing all of I/O, data, and

progr am areas . Th e I/O are a is loc ated t he lowe st add ress . The da ta a rea is provide d imme diatel y abo ve the

I/O ar ea. The da ta are a can b e divide d into reg ister, s tack , and di rect ar eas acc ording to the app licat ion. T he

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89470 series is structured as illustrated below.

Memory Space

MB89P475

General-

purpose

registers

I/O

RAM

ROM

0000H

0080H

0100H

0280H

FFFFH

0200H

Vacant

MB89475

General-

purpose

registers

I/O

RAM

ROM

0000H

0080H

0100H

0280H

FFFFH

0200H

Vacant

MB89PV470

General-

purpose

registers

I/O

RAM

0000H

0080H

0100H

FFFFH

0200H

0480H

ROM

External

(32K)

8000H

Vacant

C000HC000H

FFC0HFFC0HFFC0H

Vector table (reset, interrupt, vector call instruction)

MB89470 Series

2. Registers

The F2MC-8L famil y has tw o ty pe s of r eg ister s; de dicat ed r eg is ters i n th e CP U a nd g ene ral- pu rp ose r eg ister s

in the memory. The following registers are provided:

Program counter (PC): A 16-bit register for indicating instruction storage positions

Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator.

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX): A 16-bit register for index modification

Extra pointer (EP): A 16-bit pointer for indicating a memory address

Stack pointer (SP): A 16-bit register for indicating a stack area

Program status (PS): A 16-bit register for storing a register pointer, a condition code

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

16 bits

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

FFFDH

Undefined

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

Initial value

Structure of the Program Status Register

Vacancy Vacancy Vacancy

H I IL1, 0 N Z VC

RPPS

109876 321015 14 13 12 11

RP CCR

MB89470 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR con sists of bits indica ting the results of ar ithmetic operati ons and the conten ts of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

IL1 IL0 Interrupt level High-low

00 1High

Low = no interrupt

10 2

11 3

Rule for Conversion of Actual Addresses of the General-purpose Register Area

“0”

↓

A15

“0”

↓

A14

“0”

↓

A13

“0”

↓

A12

“0”

↓

A11

“0”

↓

A10

“0”

↓

“1”

↓

Lower OP codes

Generated addresses

MB89470 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit resister for storing data

The gen eral-pu rpos e registe rs are 8 bit s and loca ted in the registe r bank s of the memo ry. One ba nk contai ns

eight registers. Up to a total of 32 banks can be used on the MB89470 series. The bank currently in use is

indicated by the register bank pointer (RP).

This address = 0100H + 8 × (RP)

Memory area

32 banks

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

MB89470 Series

■ I/O MAP

(Continued)

Address Register name Register Description Read/Write Initial value

00HPDR0 Port 0 data register R/W XXXXXXXXB

01HDDR0 Port 0 data direction register W* 00000000B

02HPDR1 Port 1 data register R/W XXXXXXXXB

03HDDR1 Port 1 data direction register W* 00000000B

04HPDR2 Port 2 data register R/W 00000000B

05H(Reserved)

06HDDR2 Port 2 data direction register R/W 00000000B

07HSYCC System clock control register R/W -XXMM-00B

08HSTBC Standby control register R/W 0001XXXXB

09HWDTC Watchdog timer control register W* 0---XXXXB

0AHTBTC Timebase timer control register R/W 00---000B

0BHWPCR Watch prescaler control register R/W 00--0000B

0CHPDR3 Port 3 data register R/W -1111111B

0DHPDR4 Port 4 data register R -----XXXB

0EHRSFR Reset flag register R XXXX----B

0FHBUZR Buzzer register R/W -----000B

10HPDR5 Port 5 data register R/W ---XXXXXB

11HDDR5 Port 5 data direction register R/W ---00000B

12H to 13H(Reserved)

14HT4C R Timer 4 control registe r R/W 000000X0B

15HT3C R Timer 3 control registe r R/W 000000X0B

16HT4DR Timer 4 data register R/W XXXXXXXXB

17HT3DR Timer 3 data register R/W XXXXXXXXB

18HT2C R Timer 2 control registe r R/W 000000X0B

19HT1C R Timer 1 control registe r R/W 000000X0B

1AHT2DR Timer 2 data register R/W XXXXXXXXB

1BHT1DR Timer 1 data register R/W XXXXXXXXB

1CH to 1FH(Reserved)

20HADC1 A/D control register 1 R/W -00000X0B

21HADC2 A/D control register 2 R/W -0000001B

22HADDH A/D data register (Upper byte) R ------XXB

23HADDL A/D data register (Lower byte) R XXXXXXXXB

24HADER A/D input enable register R/W 11111111B

25H(Reserved)

26HSMC11 UART/SIO serial mode control register 11 R/W 00000000B

27H SMC12 UART/SIO serial mode control register 12 R/W 00000000B

28HSSD1 UART/SIO serial status and data register 1 R 00001---B

29HSIDR1/SODR1 UART/SIO serial data register 1 R/W * XXXXXXXXB

2AHSRC1 UART/SIO serial rate control register 1 R/W XXXXXXXXB

MB89470 Series

(Continued)

* Bit manipulation instruction cannot be used.

●Read/write access symbols

R/W : Readable and writable

R : Read-onl y

W: Write-only

●Initial value symbols

0: The initial value of this bit is “0”.

1: The initial value of this bit is “1”.

X: The initial value of this bit is undefined.

- : Unused bit.

M: The initial value of this bit is determined by mask option.

Address Register name Register Description Read/Write Initial value

2BHSMC21 UART serial mode control register 21 R/W 00000000B

2CHSMC22 UART serial mode control register 22 R/W 00000000B

2DHSSD2 UART serial status and data register 2 R 00001---B

2EHSIDR2/SODR2 UART serial data register 2 R/W * XXXXXXXXB

2FHSRC2 UART serial rate control register 2 R/W XXXXXXXXB

30HEIC1 External interrupt 1 control register 1 R/W 00000000B

31HEIC2 External interrupt 1 control register 2 R/W 00000000B

32HEIE2 External interrupt 2 enable register R/W ---00000B

33HEIF2 External interrupt 2 flag register R/W -------0B

34HPCR1 PWC c ontr ol register 1 R/W 0- 0--000B

35HPCR2 PWC control register 2 R/W 00000000B

36HPLBR PWC reload buffer register R/W XXXXXXXXB

37H(Reserved)

38HCNTR PWM timer control register R/W 0-00000000B

39HCOMR PWM timer compare register W* XXXXXXXXB

3AH to 6FH(Reserved)

70HPURC0 Port 0 pull up resistor control register R/W 11111111B

71HPURC1 Port 1 pull up resistor control register R/W 11111111B

72HPURC2 Port 2 pull up resistor control register R/W 11111111B

73HPURC3 Port 3 pull up resistor control register R/W -1111111B

74H(Reserved)

75HPURC5 Port 5 pull up resistor control register R/W ---1111B

76H to 7AH(Reserved)

7BHILR1 Interrupt level setting register 1 W* 1111 1111B

7CHILR2 Interrupt level setting register 2 W* 11111111B

7DHILR3 Interrupt level setting register 3 W* 11111111B

7EHILR4 Interrupt level setting register 4 W* 11111111B

7FH(Reserved)

MB89470 Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Funct ion al ope r atio n s ho ul d b e res tr icted to the c ond iti ons as detailed i n the ope ra tio nal s ections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Parameter Symbol Value Unit Remarks

Min. Max.

Power su ppl y vol tag e VCC

AVCC VSS – 0.3 VSS + 6.0 V AVCC must not exceed VCC

Input voltage VIVSS – 0.3 VCC + 0.3 V

Output voltage VOVSS – 0.3 VCC + 0.3 V

“L” level maximum output current IOL 15 mA

“L” level average output current IOLAV 4mA

Average value (operating current

× operating rate)

“L” level total maximum output

current ∑IOL 100 mA

“L” level total average output

current ∑IOLAV 40 mA Average value (operating current

× operating rate)

“H” level maximum output current IOH –15 mA

“H” level average output current IOHAV –4mA

Average value (operating current

× operating rate)

“H” level total maximum output

current ∑IOH –50 mA

“H” level total average output

current ∑IOHAV –20 mA Average value (operating current

× operating rate)

Power co nsu m pt ion PD300 mW

Operating temperature TA–40 +85 °C

Storage temperature Tstg –55 +150 °C

MB89470 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

* :These values depend on the operating conditions and the analog assurance range. See Figure 1 and

“5. A/D Converter Electrical Characteristics.”

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

Figure 1 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating

speed is switched using a gear.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC

AVCC

2.2* 5.5 V Operation assurance

range MB89475

3.5* 5.5 V Operation assurance

range MB89P475

2.7* 5.5 V Operation assurance

range MB89PV470

1.5 5.5 V Retains the RAM state in

stop mode

Operating temp er atu re TA–40 +85 °C

2.0

4.0

5.0

3.0

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Operating

Voltage (V)

4.0 2.0 1.0 0.41.33 0.8 0.66 0.57 0.50 0.44

Main clock

operating Freq. (MHz)

Min execution

time (inst. cycle) (µs)

3.5

2.7

11.0 12.0 12.5

0.36 0.33 0.32

Analog accuracy

assurance range :

Vcc = AVcc =4.5V~5.5V

5.5

2.2

4.5

Note: The shaded area is not assured for MB89P475

The dotted area is not a ssured f or MB89PV470 and MB 89P475

MB89470 Series

3. DC Characteristics

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min. Typ. Max.

“H” level

input voltage

VIH

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P40 ~ P42,

P50 ~ P54

—0.7 VCC —VCC + 0.3 V

VIHS

RST, MODE, EC1,

EC2, SCK1, SI1,

SCK2, SI2, PWC,

INT10 ~ INT13, INT20

~ INT24

—0.8 VCC —VCC + 0.3 V

“L” level

input voltage

VIL

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P40 ~ P42,

P50 ~ P54

—VSS − 0.3 —0.3 VCC V

VILS

RST, MODE, EC1,

EC2, SCK1, SI1,

SCK2, SI2, PWC,

INT10 ~ INT13, INT20

~ INT24

—VSS − 0.3 —0.2 VCC V

Open-drain

output pin

application

voltage VDP30 ~ P36 —VSS − 0.3 —VCC + 0.3 V

“H” level

output voltage VOH

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P50 ~ P54 IOH = –2.0mA 4.0 ——V

“L” level

output voltage VOL1

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P50 ~ P54, RST IOL = 4.0 mA ——0.4 V

VOL2 P30 ~ P36 IOL = 12.0 mA ——0.4 V

Input leakage

current ILI

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P50 ~ P54

0.45 V < VI <

VCC -5 —+5µAWithout

pull-up

Resister

Open drain

output leakage

current ILOD P30 ~ P36 0.45 V < VI <

VCC -5 —+5µA

Pull-down

resistance RDOWN MODE VI = VCC 25 50 100 kΩExcept

MB89P475

Pull-up

resistance RPULL

P00 ~ P07,

P10 ~ P17,

P20 ~ P27,

P30 ~ P36,

P50 ~ P54, RST

VI = 0.0 V 25 50 100 kΩ

When pull-up

resistor is

selected

(except RST)

MB89470 Series

(Continued) AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Condition Value Unit Remarks

Min. Typ. Max.

Power supply

current

ICC1

VCC

FCH = 10.0MHz

tinst = 0.4 µs

Main cl ock

run mode —813mA

ICC2

FCH = 10.0MHz

tinst = 6.4 µs

Main cl ock

run mode

—0.7 3 mA

ICCS1

FCH = 10.0MHz

tinst = 0.4 µs

Main cl ock

sleep mode —2.5 5 mA

ICCS2

FCH = 10.0MHz

tinst = 6.4 µs

Main cl ock

sleep mode —0.8 2 mA

ICCL FCL = 32.768kHz

Subclock mode —50 85 µAMB89PV470

MB89475

—350 785 µAMB89P475

ICCLS FCL = 32.768kHz

Subclock sleep

mode

—15 30 µAMB89PV470

MB89475

—19 36 µAMB89P475

ICCT

FCL = 32.768kHz

• Watch mode

• Main c lo ck stop

mode

—1.6 15 µAMB89PV470

MB89475

—5.6 21 µAMB89P475

ICCH Ta=+250C

Subclock stop

mode 310µA

AVcc FCH=10MHz —2.8 5.5 mA A/D

converting,

MB89PV470.

MB89475

—2.3 6 mA MB89P475

IAH Ta=+250C—15µA A/D stop

Input

capacitance CIN Other than

VCC,VSS,AVCC,AVSS f=1MHz —10 —pF

MB89470 Series

4. AC Characteristics

(1) Reset Timing

(VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Note: tHCYL is the oscillation cycle (1/FC) to input to the X0 pin.

The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH.

(2) Power-on Reset

(AVSS = VSS = 0.0 V , TA = –40°C to +85°C)

Note: Make sure that power supply rises within the selected oscillation stabilization time.

Rapid chan ges in po wer su pply voltag e may c ause a power- on reset. If power suppl y voltag e ne eds to

be varied in the course of operation, a smooth voltage rise is recommended.

Parameter Symbol Condition Value Unit Remarks

Min. Max.

RST “L” pulse width tZLZH —48 tHCYL —ns

Parameter Symbol Condition Value Unit Remarks

Min. Max.

Power supply rising time tR——50 ms

Power supply cut-off time tOFF 1—ms Due to repeated operations

tZLZH

0.2 VCC 0.2 VCC

RST

0.2 V 0.2 V

3.5 V

0.2 V

tOFF

MB89470 Series

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Value Unit Remarks

Min. Typ. Max.

Clock freque nc y FCH X0, X1 1 —12.5 MHz

FCL X0A, X1A —32.768 —kHz

Clock cy cle time tHCYL X0, X1 80 —1000 ns

tLCYL X0A, X1A —30.5 —µs

Input clock pulse width

PWH

PWL X0 20 ——ns

External clock

PWHL

PWLL X0A —15.2 —µs

Input clock rising/falling time tCR

tCF X0, X0A ——10 ns

0.2

0.8

X0 0.2

0.8

0.2

X0 X1 X0 X1

When a crystal

ceramic reasonator is used When an external clock is used

Open

HCYL

C1 C2 F

X0 and X1 Timing and Conditions

Main Clock Conditions

MB89470 Series

(4) Instruction Cycle

Parameter Symbol Value Unit Remarks

Instruction cycle

(minim um execution time) tinst

4/FCH, 8/FCH, 16/FCH, 64/FCH µs(4/FCH)tinst = 0.32 µs when operating

at FCH = 12.5 MHz

2/FCL µstinst = 61.036 µs when operating at

FCL = 32.768 kHz

X0A X1A

C0C1

Rd Open

When a crystal

ceramic oscillator is used When sub-clock is not used in dual clock product

X0A X1A

FCL

0.8

LCYL

0.2

WHL

WLL

X0A

Open

When an external clock is used

FCL

X0A X1A

Subclock Timing and Conditions

Subclock Conditions

MB89470 Series

(5) Serial I/O Timing

(VCC = 5.0 V, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

Parameter Symbol Pin Condition Value Unit

Min. Max.

Serial clock cycle time tSCYC SCK1, SCK2 Internal

shift clock

mode

2 tinst*—µs

SCK ↓ → SO time tSLOV SCK1, SO1, SCK2, SO2, –200 200 ns

Valid SI → SCK ↑tIVSH SI1, SCK1, SI2, SCK2 1/2 tinst*—ns

SCK ↑ → valid SI hold time tSHIX SCK1, SI1, SCK2, SI2 1/2 tinst*—ns

Serial cloc k “H” puls e width tSHSL SCK1, SCK2 External

shift clock

mode

1 tinst*—µs

Seri al cl oc k “L” pulse width tSLSH 1 tinst*—µs

SCK ↓ → SO time tSLOV SCK1, SO1, SCK2, SO2 0 200 ns

Valid SI → SCK ↑tIVSH SI1, SCK1, SI2, SCK2 1/2 tinst*—ns

SCK ↑ → valid SI hold time tSHIX SCK1, SI1, SCK2, SI2 1/2 tinst*—ns

0.2 VCC

0.8 VCC

tSLSH

2.4 V

0.2 VCC

0.8 VCC

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

SCK

0.2 VCC

tSHSL

tSHIX

tIVSH

tSLOV

External Clock Operation

0.8 V

2.4 V

tSCYC

2.4 V

0.2 VCC

tSHIX

0.8 V

tIVSH

0.8 VCC

0.2 VCC

0.8 VCC

SCK

tSLOV

Internal Clock Operation

MB89470 Series

(6) Peripheral Input Timing

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

Parameter Symbol Pin Value Unit Remarks

Min. Max.

Peripheral input “H” pulse width 1 tILIH1 INT10 ~ 13, INT20 ~

INT24, EC1, EC2, PWC 2 tinst*—µs

Peripheral input “L” pulse width 1 tIHIL1 2 tinst*—µs

0.2 VCC

0.8 VCC

t IHIL1

0.8 VCC

INT10 to 13,

INT20 to 24,

EC1, EC2,

PWC 0.2 VCC

t ILIH1

MB89470 Series

5. A/D Converter Electrical Characterist ics

(1) A/D Converter Electrical Characteristics

(AVCC = VCC = 4.5 V ~ 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics".

(2) A/D Converter Glossary

•Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 210 = 1024.

•Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point ("00 0000 0000" ↔ "00 0000 0001") with

the full-scale transition point ("11 1111 1111" ↔ "11 1111 1110") from actual conversion characteristics.

•Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.

•Total error (unit: LSB)

The difference between theoretical and actual conversion values.

Parameter Symbol Pin Value Unit Remarks

Min. Typ. Max.

Resolution

—

—10 —bit

Total error ——±3.0 LSB

Linearity error ——±2.5 LSB

Dif fere nti al lin ear ity error ——±1.9 LSB

Zero transition voltage VOT AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB LSB

Full-scale transition

voltage VFST AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC + 0.5 LSB LSB

A/D mode co nversion time ———60 tinst* µs

Analog p ort input current IAIN AN0 to

AN3 ——10 µA

Analog input voltage VAIN AVSS —AVCC V

MB89470 Series

0.5 LSB

1 LSB

Analog input

AVSS

1.5 LSB

Theoretical I/O characteristics

3FF

3FE

3FD

004

003

002

001

AVCC

Theoretical value

Analog input

AVSS

VNT

Actual conversion

value

Total error

3FF

3FE

3FD

004

003

002

001

AVCC

{1 LSB × N + V

}

VFST

VOT Actual conversion

value

Total error = VNT – {1 LSB × N + 0.5 LSB}

1 LSB

1 LSB = VFST – VOT

1022

Digital output

(V)

Analog input

AVSS

Linearity error

3FF

3FE

3FD

004

003

002

001

AVCC

Theoretical value

Analog input

AVSS

VNT

V(N + 1)T

Actual conversion

value

Differential linearity error

N + 1

N – 1

N – 2

AVCC

VOT (Actual measurement)

Actual conversion value

Differential linearity error = 1 LSB

V(N + 1)T – VNT

Digital output

Linearity error = VNT – {1 LSB × N + VOT}

1 LSB – 1

{1 LSB × N + VOT}

Actual conversion

value

VFST

(Actual

measurement)

Theoretical value

Analog input

AVSS

Zero transition error

004

003

002

001

Theoretical value

Analog input

Actual conversion

value

Full-scale transition error

AVCC

Actual conversion value

Digital output

Actual conversion

value

Actual conversion

value

VOT (Actual measurement)

VFST

(Actual

measurement)

3FF

3FE

3FD

3FC

MB89470 Series

(3) Notes on Using A/D Converter

•Input impedance of the analog input pins

The A/D co nverter used for the MB 89470 series conta ins a sample hold c ircuit as illustrate d below to fetch

analog input voltage into the sample hold capacitor for 16 instruction cycles after activation A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabiliz e withi n th e analog in put s am pl ing period. The ref ore, i t is rec omm end ed to keep th e ou tput

impedance of the external circuit low.

Note that if the impedanc e cann ot be kept lo w, it is recomm ended to c onnect an ex ternal cap acito r of about

0.1 µF for the analog input pin.

•Error

The smaller the |AVR - AVSS|, the greate r the error would bec ome rela tivel y.

MB89475

MB89PV470 MB89P475

R: analog input equivalent resistance 2.2 kΩ2.6 kΩ

C: analog input equivalent capacitance 45 pF 28 pF

Analog input pin

Sample hold circuit

If the analog input

impedance is too low,

it is recommended to

connect an external

capacitor of approx.

0.1 µF.

Comparator

R C

Analog channel selector

Close for 16 instruction cycles after

activating A/D conversion.

Analog Input Circuit Model

MB89470 Series

■INSTRUCTIONS

Execution instructions can be divided into the following four groups:

•Transfer

•Arithm etic ope ra tio n

•Branch

•Others

Table 1 lists symbols used for notation of instructions.

(Continued)

Table 1 Instruction Symbols

Symbol Meaning

dir Direct address (8 bits)

off Offset (8 bits)

ext Extended address (16 bits)

#vct Vector table number (3 bits)

#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)

dir: b Bit direct address (8:3 bits)

rel Branch relative address (8 bits)

@ Register indirect (Example: @A, @IX, @EP)

A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

AH Upper 8 bits of accumulator A (8 bits)

AL Lower 8 bits of accumulator A (8 bits)

TTemporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

TH Upper 8 bits of temporary accumulator T (8 bits)

TL Lower 8 bits of temporary accumulator T (8 bits)

IX Index register IX (16 bits)

MB89470 Series

(Continued)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~: Number of instructions

#: Number of bytes

Operation: Operation of an instruction

TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

•“–” indicates no change.

•dH is the 8 upper bits of operation description data.

•AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

•00 becomes 00.

N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

OP code: Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

Symbol Meaning

EP Extra pointer EP (16 bits)

PC Program counter PC (16 bits)

SP Stack pointer SP (16 bits)

PS Program status PS (16 bits)

dr Accumulator A or index register IX (16 bits)

CCR Condition code register CCR (8 bits)

RP Register bank pointer RP (5 bits)

Ri General-purpose register Ri (8 bits, i = 0 to 7)

×Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × ) Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

(( × )) The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

MB89470 Series

Notes: •During byte transfer to A, T ← A is restricted to low bytes.

•Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F2MC-8 family)

Table 2 Transfer Instructions (48 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

SETB dir: b

CLRB dir: b

XCH A,T

XCHW A,T

XCHW A,E P

XCHW A,IX

XCHW A,S P

MOVW A,PC

(dir) ← (A)

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

(A) ← (Ri)

(dir) ← d8

( (IX) +off ) ← d8

( (EP) ) ← d8

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (A L)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

– – – –

+ + – –

– – – –

+ + – –

– – – –

+ + + +

– – – –

48 to 4F

08 to 0F

88 to 8F

A8 to AF

A0 to A7

MB89470 Series

(Continued)

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

ROLC A

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

DAS

XOR A

XOR A,# d8

XOR A,d ir

XOR A,@ EP

XOR A,@ IX +o ff

XOR A,Ri

AND A

AND A,#d8

AND A,dir

(A) ← (A) + (Ri) + C

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) ∧ (T)

(A) ← (A) ∨ (T)

(A) ← (A) ∀ (T)

(TL) − (AL)

(T) − (A)

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) ∀ (TL)

(A) ← (AL) ∀ d8

(A) ← (AL) ∀ (dir)

(A) ← (AL) ∀ ( (EP) )

(A) ← (AL) ∀ ( (IX) +off)

(A) ← (AL) ∀ (Ri)

(A) ← (AL) ∧ (TL )

(A) ← (AL) ∧ d8

(A) ← (AL) ∧ (dir)

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

+ + + +

+ + R –

28 to 2F

38 to 3F

C8 to CF

D8 to DF

18 to 1F

58 to 5F

←

→→

MB89470 Series

(Continued)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

DECW SP

(A) ← (AL) ∧ ( (EP) )

(A) ← (AL) ∧ ( (IX) +off)

(A) ← (AL) ∧ (Ri)

(A) ← (AL) ∨ (TL)

(A) ← (AL) ∨ d8

(A) ← (AL) ∨ (dir)

(A) ← (AL) ∨ ( (EP) )

(A) ← (AL) ∨ ( (IX) +off)

(A) ← (AL) ∨ (Ri)

(dir) – d8

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

–

+ + R –

+ + + +

– – – –

68 to 6F

78 to 7F

98 to 9F

Table 4 Branch Instructions (17 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BL O re l

BNC/BHS rel

BN rel

BP rel

BLT r el

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

RETI

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V ∀ N = 1 then PC ← PC + rel

If V ∀ N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

– – – –

– + – –

– – – –

Restore

B0 to B7

B8 to BF

E8 to EF

Table 5 Other Instructions (9 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

CLRI

SETI

–

– – – –

– – – R

– – – S

– – – –

MB89470 Series

■ INSTRUCTION MAP

0123456789ABCDEF

0NOP SWAP RET RETI PUSHWAPOPW AMOV

A,ext MOVW

A,PS CLRI SETI CLRB

dir: 0 BBC

dir: 0,rel INCW ADECW AJMP @A MOVW

A,PC

1MULU ADIVU AJMP

addr16 CALL

addr16 PUSHW

IX POPWIX MOV

ext,A MOVW

PS,A CLRC SETC CLRB

dir: 1 BBC

dir: 1,rel INCWSP DECWSP MOVW

SP,A MOVW

A,SP

2ROLC ACMP AADDC ASUBC AXCH A, T XOR AAND AOR AMOV

@A,T MOV

A,@A CLRB

dir: 2 BBC

dir: 2,rel INCW IX DECWIX MOVW

IX,A MOVW

A,IX

3RORC ACMPW AADDCW

ASUBCWAXCHW

A, T XORW AANDW AORW AMOVW

@A,T MOVW

A,@A CLRB

dir: 3 BBC

dir: 3,rel INCWEP DECWEP MOVW

EP,A MOVW

A,EP

4MOV

A,#d8 CMP

A,#d8 ADDC

A,#d8 SUBC

A,#d8 XOR

A,#d8 AND

A,#d8 ORA,#d8 DAA DAS CLRB

dir: 4 BBC

dir: 4,rel MOVW

A,ext MOVW

ext,A MOVW

A,#d16 XCHW

A,PC

5MOVA,dir CMPA,dir ADDC

A,dir SUBC

A,dir MOVdir,A XORA,dir ANDA,dir OR A,dir MOV

dir,#d8 CMP

dir,#d8 CLRB

dir: 5 BBC

dir: 5,rel MOVW

A,dir MOVW

dir,A MOVW

SP,#d16 XCHW

A,SP

6MOV

A,@I X

CMP

A,@IX

ADDC

A,@I X

SUBC

A,@IX

MOV

@IX

+d,A

XOR

@A,IX

AND

A,@IX

MOV@IX

+d,#d8

CMP@IX

+d,#d8

CLRB

dir: 6 BBC

dir: 6,rel MOVW

A,@IX

MOVW

@IX

+d,A

MOVW

IX,#d16 XCHW

A,IX

7MOV

A,@EP CMP

A,@EP ADDC

A,@EP SUBC

A,@EP MOV

@EP,A XOR

A,@EP AND

A,@EP OR

A,@EP MOV

@EP,#d8 CMP

@EP,#d8 CLRB

dir: 7 BBC

dir: 7,rel MOVW

A,@EP MOVW

@EP,A MOVW

EP,#d16 XCHW

A,EP

8MOV

A,R0 CMP

A,R0 ADDC

A,R0 SUBC

A,R0 MOV

R0,A XORA,R0 ANDA,R0 OR A,R0 MOV

R0,#d8 CMP

R0,#d8 SETB

dir: 0 BBS

dir: 0,rel INC R0 DEC R0 CALLV

#0 BNC rel

9MOV

A,R1 CMP

A,R1 ADDC

A,R1 SUBC

A,R1 MOV

R1,A XORA,R1 ANDA,R1 OR A,R1 MOV

R1,#d8 CMP

R1,#d8 SETB

dir: 1 BBS

dir: 1,rel INC R1 DEC R1 CALLV#1 BC rel

AMOV

A,R2 CMP

A,R2 ADDC

A,R2 SUBC

A,R2 MOV

R2,A XORA,R2 ANDA,R2 OR A,R2 MOV

R2,#d8 CMP

R2,#d8 SETB

dir: 2 BBS

dir: 2,rel INC R2 DEC R2 CALLV#2 BP rel

BMOV

A,R3 CMP

A,R3 ADDC

A,R3 SUBC

A,R3 MOV

R3,A XORA,R3 ANDA,R3 OR A,R3 MOV

R3,#d8 CMP

R3,#d8 SETB

dir: 3 BBS

dir: 3,rel INC R3 DEC R3 CALLV#3 BN rel

CMOV

A,R4 CMP

A,R4 ADDC

A,R4 SUBC

A,R4 MOV

R4,A XORA,R4 ANDA,R4 OR A,R4 MOV

R4,#d8 CMP

R4,#d8 SETB

dir: 4 BBS

dir: 4,rel INC R4 DEC R4 CALLV

#4 BNZ rel

DMOV

A,R5 CMP

A,R5 ADDC

A,R5 SUBC

A,R5 MOV

R5,A XORA,R5 ANDA,R5 OR A,R5 MOV

R5,#d8 CMP

R5,#d8 SETB

dir: 5 BBS

dir: 5,rel INC R5 DEC R5 CALLV#5 BZ rel

EMOV

A,R6 CMP

A,R6 ADDC

A,R6 SUBC

A,R6 MOV

R6,A XORA,R6 ANDA,R6 OR A,R6 MOV

R6,#d8 CMP

R6,#d8 SETB

dir: 6 BBS

dir: 6,rel INC R6 DEC R6 CALLV

#6 BGE rel

FMOV

A,R7 CMP

A,R7 ADDC

A,R7 SUBC

A,R7 MOV

R7,A XORA,R7 ANDA,R7 OR A,R7 MOV

R7,#d8 CMP

R7,#d8 SETB

dir: 7 BBS

dir: 7,rel INC R7 DEC R7 CALLV

#7 BLT rel

MB89470 Series

■MASK OPTIONS

■ORDERING INFORMATION

No. Part number MB89475 MB89P475 MB89PV470

Specify in g procedur e Specify when

ordering masking Setting not possible Setting not possible

1Selection of clock mode

• Single clock mode

• Dual clock mode Selectable 101/102: Single clock

201/202: Dual clock 101: Single clock

201: Dual clock

Selection of OTPROM content

protection feature

•No protection feature

•With protection feature

-- 101/201: No protection

102/202: with protection --

Selection of oscillation stabilization

time (OSC)

•The initial value of the oscillation

stabilization time for the main

clock can be set by selecting the

values of the WTM1 and WTM0

bits on the right.

Selectable

OSC

1 : 214/FCH

2 : 217/FCH

3 : 218/FCH

Fixed to oscillation

stabilization time of

218/FCH

Fixed to oscillation

stabilization time of

218/FCH

Selection of power-on stabilization

time

•Nil

•217/FCH

Selectable Fixed to power-on

stabilization time of

217/FCH Fixed to nil

Part number P ack age Remar ks

MB89475PFV

MB89P475PFV-101

MB89P475PFV-102

MB89P475PFV-201

MB89P475PFV-202

48-pin Pl as tic QFP

(FPT-48P-M05) 101: Single clock, without

content protection

102: Single clock, with

content protection

201: Dual cloc k, with out

content protection

202: Dual cloc k, with

content protection

MB89475P-SH

MB89P475P-SH-101

MB89P475P-SH-102

MB89P475P-SH-201

MB89P475P-SH-202

48-pin Plastic SH-DIP

(DIP-48P-M01)

MB89PV470CF-101

MB89PV470CF-201 48-pin Cerami c MQFP

(MQP-48C-P01)

MB89470 Series

■PACKAGE DIMENSIONS

1994 FUJITSU LIMITED D48002S-3C-3

43.69

+0.20

–0.30

+.008

–.012

1.720

13.80±0.25

(.543±.010)

INDEX-1

5.25(.207)

3.00(.118)

0.45±0.10

(.018±.004)

+.020

–0

.039

–0

+0.50

1.00

1.778±0.18

(.070±.007)

1.778(.070)

MAX

0.25±0.05

(.010±.002)

15.24(.600)

TYP 15°MAX

INDEX-2

40.894(1.610)REF

MAX

MIN

0.51(.020)MIN

Dimensions in mm (inches)

48-pin Plastic SH-DIP

DIP-48P-M01

2000 FUJITSU LIMITED F48013S-c-4-8

36 25

INDEX

7.00±0.10(.276±.004)SQ

9.00±0.20(.354±.008)SQ

0.145±0.055

(.006±.002)

0.08(.003)

"A" 0°~8°

.059 –.004

+.008

–0.10

+0.20

1.50

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

(Stand off)

0.25(.010)

Details of "A" part

1 12

0.08(.003) M

(.008±.002)

0.20±0.05

0.50(.020)

LEAD No.

(Mounting height)

48-pi n Plast ic LQFP

FPT-48P-M05

Dimensions in mm (inches)

MB89470 Series

–.010

+.018

–0.25

+0.45

+0.13

–0.0

+.005

–0

PIN No.1 INDEX

1.50(.059)TYP

1.00(.040)TYP

8.80(.346)REF

(.0315±.0087)

0.80±0.22

(.016±.003)

0.40±0.08

.043

1.10 0.60(.024)TYP

8.50(.335)MAX

(.006±.002)

0.15±0.05

PAD No.1 INDEX

4.50(.177)TYP

0.30(.012)TYP

TYP TYP

8.71(.343)

7.14(.281)

(.040±.005)

1.02±0.13

10.92

.430

PIN No.1 INDEX

17.20(.677)TYP

(.591±.010)

15.00±0.25

(.583±.014)

14.82±0.35

1994 FUJITSU LIMITED M48001SC-4-2

48-pin Ceramic MQFP

MQP-48C-P01

Dimensions in mm (inches)

MB89470 Series

MEMO

MB89470 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: (044) 754-3763

Fax: (044) 754-3329

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866- 860 8

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreie ic h-Bu chsc hlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE L TD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

http://www.fmap.com.sg/

Circuit diagrams utilizing Fujitsu products are included as a

means of illustrating typical semiconductor applications.

Complete information sufficient for construction purposes is not

necessar ily given.

The info rmation contai ned in th is document has been care fully

checked and is believed to be reliable. However, Fujitsu

assumes no responsibility for inaccuracies.

The information contained in this document does not convey any

license under the copyrights, patent rights or trademarks claimed

and owned by Fujitsu.

Fujitsu reserves the right to change products or specifications

without notice.

No part of this p ublica tio n may be copied or repr oduced i n any

form or by any means, or transferred to any third party without

prior written consent of Fujitsu.

The infor mation c ontain ed in this docu ment a re not i ntended fo r

use with equipments which require extremely high reliability

such as aerospace equipments, undersea repeaters, nuclear

contro l syst ems or medical eq ui pments for life sup port.